use work.textmode_vga_pkg.all;
use work.textmode_vga_platform_dependent_pkg.all;
use work.ps2_keyboard_controller_pkg.all;
+use work.sync_pkg.all;
entity calc is
port (
CLK_50MHZ : in std_logic;
sys_res : in std_logic;
- -- btnA
- -- TODO: pins
+ -- btnA (here: "btn west")
+ btn_a : in std_logic;
-- rs232
- -- TODO: pins
+ rxd : in std_logic;
+ txd : out std_logic;
-- vga
vsync_n : out std_logic;
hsync_n : out std_logic;
b : out std_logic_vector(BLUE_BITS - 1 downto 0);
-- ps/2
ps2_clk : inout std_logic;
- ps2_data : inout std_logic;
- -- debug
- led0 : out std_logic;
- led1 : out std_logic
+ ps2_data : inout std_logic
);
end entity calc;
signal p_wdone : std_logic;
signal p_write : hbyte;
signal p_finished : std_logic;
+ --history/pc_com
+ signal pc_get : std_logic;
+ signal pc_spalte : hspalte;
+ signal pc_zeile : hzeile;
+ signal pc_char : hbyte;
+ signal pc_done : std_logic;
+ signal pc_busy : std_logic;
-- parser/scanner
signal do_it, finished : std_logic;
+ -- rs232
+ signal rx_new, rxd_sync : std_logic;
+ signal rx_data : std_logic_vector (7 downto 0);
+ signal tx_new, tx_done : std_logic;
+ signal tx_data : std_logic_vector (7 downto 0);
begin
- led0 <= '0';
- led1 <= '1';
sys_res_n <= not sys_res;
-- vga/ipcore
p_wtake => p_wtake,
p_wdone => p_wdone,
p_write => p_write,
- p_finished => p_finished
+ p_finished => p_finished,
+ -- pc communication
+ pc_get => pc_get,
+ pc_spalte => pc_spalte,
+ pc_zeile => pc_zeile,
+ pc_char => pc_char,
+ pc_busy => pc_busy,
+ pc_done => pc_done
);
-- parser
ps2_clk => ps2_clk,
ps2_data => ps2_data
);
+
+ -- synchronizer fuer rxd
+ sync_rxd_inst : entity work.sync(beh)
+ generic map (
+ SYNC_STAGES => 2,
+ RESET_VALUE => '1'
+ )
+ port map (
+ sys_clk => CLK_50MHZ,
+ sys_res_n => sys_res_n,
+ data_in => rxd,
+ data_out => rxd_sync
+ );
+
+ -- rs232-rx
+ rs232rx_inst : entity work.uart_rx(beh)
+ generic map (
+ CLK_FREQ => 50000000,
+ BAUDRATE => 115200
+ )
+ port map (
+ sys_clk => CLK_50MHZ,
+ sys_res_n => sys_res_n,
+ rxd => rxd_sync,
+ rx_data => rx_data,
+ rx_new => rx_new
+ );
+
+ -- rs232-tx
+ rs232tx_inst : entity work.uart_tx(beh)
+ generic map (
+ CLK_FREQ => 50000000,
+ BAUDRATE => 115200
+ )
+ port map (
+ sys_clk => CLK_50MHZ,
+ sys_res_n => sys_res_n,
+ txd => txd,
+ tx_data => tx_data,
+ tx_new => tx_new,
+ tx_done => tx_done
+ );
+
+ -- pc-com
+ pc_com_inst : entity work.pc_communication(beh)
+ port map (
+ sys_clk => CLK_50MHZ,
+ sys_res_n => sys_res_n,
+ --button
+ btn_a => not btn_a,
+ --uart_tx
+ tx_data => tx_data,
+ tx_new => tx_new,
+ tx_done => tx_done,
+ --uart_rx
+ rx_data => rx_data,
+ rx_new => rx_new,
+ -- History
+ pc_zeile => pc_zeile,
+ pc_spalte => pc_spalte,
+ pc_get => pc_get,
+ pc_busy => pc_busy,
+ pc_done => pc_done,
+ pc_char => pc_char
+ );
end architecture top;