entity calc is
port (
CLK_50MHZ : in std_logic;
- -- sys_res_n : in std_logic;
+ sys_res : in std_logic;
-- btnA
-- TODO: pins
-- rs232
end entity calc;
architecture top of calc is
+ -- reset
+ signal sys_res_n : std_logic;
-- ps/2
signal new_data : std_logic;
signal data : std_logic_vector(7 downto 0);
begin
led0 <= '0';
led1 <= '1';
+ sys_res_n <= not sys_res;
-- vga/ipcore
textmode_vga_inst : entity work.textmode_vga(struct)
)
port map (
sys_clk => CLK_50MHZ,
- sys_res_n => '1',
+ sys_res_n => sys_res_n,
command => command,
command_data => command_data,
free => free,
vga_clk => vga_clk,
- vga_res_n => '1',
+ vga_res_n => sys_res_n,
vsync_n => vsync_n,
hsync_n => hsync_n,
r => r,
display_inst : entity work.display(beh)
port map (
sys_clk => CLK_50MHZ,
- sys_res_n => '1',
+ sys_res_n => sys_res_n,
-- history
d_new_eingabe => d_new_eingabe,
d_new_result => d_new_result,
history_inst : entity work.history(beh)
port map (
sys_clk => CLK_50MHZ,
- sys_res_n => '1',
+ sys_res_n => sys_res_n,
-- scanner
s_char => s_char,
s_take => s_take,
scanner_inst : entity work.scanner(beh)
port map (
sys_clk => CLK_50MHZ,
- sys_res_n => '1',
+ sys_res_n => sys_res_n,
-- ps/2
new_data => new_data,
data => data,
)
port map (
sys_clk => CLK_50MHZ,
- sys_res_n => '1',
+ sys_res_n => sys_res_n,
-- scanner
new_data => new_data,
data => data,