spartan3e: reset-button

diff --git a/spartan3e/spartan3e.ucf b/spartan3e/spartan3e.ucf
index f87cd5543f4ee1e26730e430f7efda61f5354b8a..fc193cd85267cccb69e54683dd34b31b4b4d4f49 100644 (file)
--- a/spartan3e/spartan3e.ucf
+++ b/spartan3e/spartan3e.ucf
@@ -12,7 +12,7 @@
 # ==== Pushbuttons (BTN) ====
 #NET "BTN_EAST" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ;
 #NET "BTN_NORTH" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN ;
-#NET "BTN_SOUTH" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
+NET "sys_res" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
 #NET "BTN_WEST" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ;
 # ==== Clock inputs (CLK) ====
 NET "CLK_50MHZ" LOC = "C9" | IOSTANDARD = LVCMOS33 ;

diff --git a/src/calc_s3e.vhd b/src/calc_s3e.vhd
index bc1cc090142e347cdad0a56bb4fac458e2108c57..db81c548a0d27b47ed294b0b2f2225778c9e8ed4 100644 (file)
--- a/src/calc_s3e.vhd
+++ b/src/calc_s3e.vhd
@@ -10,7 +10,7 @@ use work.ps2_keyboard_controller_pkg.all;
 entity calc is
        port (
                CLK_50MHZ : in std_logic;
-               -- sys_res_n : in std_logic;
+               sys_res : in std_logic;
                -- btnA
                -- TODO: pins
                -- rs232
@@ -31,6 +31,8 @@ entity calc is
 end entity calc;
 
 architecture top of calc is
+       -- reset
+       signal sys_res_n : std_logic;
        -- ps/2
        signal new_data : std_logic;
        signal data : std_logic_vector(7 downto 0);
@@ -54,6 +56,7 @@ architecture top of calc is
 begin
        led0 <= '0';
        led1 <= '1';
+       sys_res_n <= not sys_res;
 
        -- vga/ipcore
        textmode_vga_inst : entity work.textmode_vga(struct)
@@ -64,12 +67,12 @@ begin
        )
        port map (
                sys_clk => CLK_50MHZ,
-               sys_res_n => '1',
+               sys_res_n => sys_res_n,
                command => command,
                command_data => command_data,
                free => free,
                vga_clk => vga_clk,
-               vga_res_n => '1',
+               vga_res_n => sys_res_n,
                vsync_n => vsync_n,
                hsync_n => hsync_n,
                r => r,
@@ -88,7 +91,7 @@ begin
        display_inst : entity work.display(beh)
        port map (
                sys_clk => CLK_50MHZ,
-               sys_res_n => '1',
+               sys_res_n => sys_res_n,
                -- history
                d_new_eingabe => d_new_eingabe,
                d_new_result => d_new_result,
@@ -108,7 +111,7 @@ begin
        history_inst : entity work.history(beh)
        port map (
                sys_clk => CLK_50MHZ,
-               sys_res_n => '1',
+               sys_res_n => sys_res_n,
                -- scanner
                s_char => s_char,
                s_take => s_take,
@@ -132,7 +135,7 @@ begin
        scanner_inst : entity work.scanner(beh)
        port map (
                sys_clk => CLK_50MHZ,
-               sys_res_n => '1',
+               sys_res_n => sys_res_n,
                -- ps/2
                new_data => new_data,
                data => data,
@@ -154,7 +157,7 @@ begin
        )
        port map (
                sys_clk => CLK_50MHZ,
-               sys_res_n => '1',
+               sys_res_n => sys_res_n,
                -- scanner
                new_data => new_data,
                data => data,