gesamt: parser ins historymodul eingebaut und es geht, YEAH! :)

[hwmod.git] / src / calc_s3e.vhd

diff --git a/src/calc_s3e.vhd b/src/calc_s3e.vhd
index 636128fc8555d58528f94b50f1821b1bca516659..c43749d699d003a3243024e65159bc9dd5d3d3fc 100644 (file)
--- a/src/calc_s3e.vhd
+++ b/src/calc_s3e.vhd
@@ -9,8 +9,8 @@ use work.ps2_keyboard_controller_pkg.all;
 
 entity calc is
        port (
-               sys_clk_real : in std_logic;
-               sys_res_n : in std_logic;
+               CLK_50MHZ : in std_logic;
+               sys_res : in std_logic;
                -- btnA
                -- TODO: pins
                -- rs232
@@ -31,8 +31,8 @@ entity calc is
 end entity calc;
 
 architecture top of calc is
-       -- clk
-       signal sys_clk : std_logic;
+       -- reset
+       signal sys_res_n : std_logic;
        -- ps/2
        signal new_data : std_logic;
        signal data : std_logic_vector(7 downto 0);
@@ -42,7 +42,7 @@ architecture top of calc is
        signal command : std_logic_vector(COMMAND_SIZE - 1 downto 0);
        signal command_data : std_logic_vector(3 * COLOR_SIZE + CHAR_SIZE -1 downto 0);
        -- history/display
-       signal d_new_eingabe, d_new_result : std_logic;
+       signal d_new_eingabe, d_new_result, d_new_bs : std_logic;
        signal d_zeile : hzeile;
        signal d_spalte : hspalte;
        signal d_get, d_done : std_logic;
@@ -50,24 +50,20 @@ architecture top of calc is
        -- history/scanner
        signal s_char : hbyte;
        signal s_take, s_done, s_backspace : std_logic;
-
-       -- tmp: history<>scanner
+       -- history/parser
+       signal p_rget : std_logic;
+       signal p_rdone : std_logic;
+       signal p_read : hbyte;
+       signal p_wtake : std_logic;
+       signal p_wdone : std_logic;
+       signal p_write : hbyte;
+       signal p_finished : std_logic;
+       -- parser/scanner
        signal do_it, finished : std_logic;
-
-       COMPONENT dcm_s3e
-       PORT(
-               CLKIN_IN : IN std_logic;
-               RST_IN : IN std_logic;
-               CLKIN_IBUFG_OUT : OUT std_logic;
-               CLK0_OUT : OUT std_logic;
-               CLK0_OUT1 : OUT std_logic;
-               LOCKED_OUT : OUT std_logic
-               );
-       END COMPONENT;
-
 begin
        led0 <= '0';
        led1 <= '1';
+       sys_res_n <= not sys_res;
 
        -- vga/ipcore
        textmode_vga_inst : entity work.textmode_vga(struct)
@@ -77,7 +73,7 @@ begin
                SYNC_STAGES => 2
        )
        port map (
-               sys_clk => sys_clk,
+               sys_clk => CLK_50MHZ,
                sys_res_n => sys_res_n,
                command => command,
                command_data => command_data,
@@ -92,23 +88,21 @@ begin
        );
 
        -- pll fuer vga
-       dcm_s3e_inst : dcm_s3e PORT MAP(
-               CLKIN_IN => sys_clk_real,
-               RST_IN => sys_res_n,
-               CLKIN_IBUFG_OUT => sys_clk,
-               CLK0_OUT => vga_clk,
-               CLK0_OUT1 => open,
-               LOCKED_OUT => open
+       clk_vga_s3e_inst : entity work.clk_vga_s3e(beh)
+       port map (
+               clk50 => CLK_50MHZ,
+               clk25 => vga_clk
        );
 
        -- display
        display_inst : entity work.display(beh)
        port map (
-               sys_clk => sys_clk,
+               sys_clk => CLK_50MHZ,
                sys_res_n => sys_res_n,
                -- history
                d_new_eingabe => d_new_eingabe,
                d_new_result => d_new_result,
+               d_new_bs => d_new_bs,
                d_zeile => d_zeile,
                d_spalte => d_spalte,
                d_get => d_get,
@@ -123,7 +117,7 @@ begin
        -- history
        history_inst : entity work.history(beh)
        port map (
-               sys_clk => sys_clk,
+               sys_clk => CLK_50MHZ,
                sys_res_n => sys_res_n,
                -- scanner
                s_char => s_char,
@@ -133,12 +127,36 @@ begin
                -- display
                d_new_eingabe => d_new_eingabe,
                d_new_result => d_new_result,
+               d_new_bs => d_new_bs,
                d_zeile => d_zeile,
                d_spalte => d_spalte,
                d_get => d_get,
                d_done => d_done,
                d_char => d_char,
-               -- TODO: tmp only!
+               -- parser
+               p_rget => p_rget,
+               p_rdone => p_rdone,
+               p_read => p_read,
+               p_wtake => p_wtake,
+               p_wdone => p_wdone,
+               p_write => p_write,
+               p_finished => p_finished
+       );
+
+       -- parser
+       parser_inst : entity work.parser(beh)
+       port map (
+               sys_clk => CLK_50MHZ,
+               sys_res_n => sys_res_n,
+               -- history
+               p_rget => p_rget,
+               p_rdone => p_rdone,
+               p_read => p_read,
+               p_wtake => p_wtake,
+               p_wdone => p_wdone,
+               p_write => p_write,
+               p_finished => p_finished,
+               -- scanner
                do_it => do_it,
                finished => finished
        );
@@ -146,7 +164,7 @@ begin
        -- scanner
        scanner_inst : entity work.scanner(beh)
        port map (
-               sys_clk => sys_clk,
+               sys_clk => CLK_50MHZ,
                sys_res_n => sys_res_n,
                -- ps/2
                new_data => new_data,
@@ -156,7 +174,7 @@ begin
                s_take => s_take,
                s_done => s_done,
                s_backspace => s_backspace,
-               -- TODO: parser. temporaer mit history verbunden
+               -- parser
                do_it => do_it,
                finished => finished
        );
@@ -168,7 +186,7 @@ begin
                SYNC_STAGES => 2
        )
        port map (
-               sys_clk => sys_clk,
+               sys_clk => CLK_50MHZ,
                sys_res_n => sys_res_n,
                -- scanner
                new_data => new_data,