history/display: backspace logic

[hwmod.git] / src / calc_s3e.vhd

diff --git a/src/calc_s3e.vhd b/src/calc_s3e.vhd
index 636128fc8555d58528f94b50f1821b1bca516659..bc1cc090142e347cdad0a56bb4fac458e2108c57 100644 (file)
--- a/src/calc_s3e.vhd
+++ b/src/calc_s3e.vhd
@@ -9,8 +9,8 @@ use work.ps2_keyboard_controller_pkg.all;
 
 entity calc is
        port (
-               sys_clk_real : in std_logic;
-               sys_res_n : in std_logic;
+               CLK_50MHZ : in std_logic;
+               -- sys_res_n : in std_logic;
                -- btnA
                -- TODO: pins
                -- rs232
@@ -31,8 +31,6 @@ entity calc is
 end entity calc;
 
 architecture top of calc is
-       -- clk
-       signal sys_clk : std_logic;
        -- ps/2
        signal new_data : std_logic;
        signal data : std_logic_vector(7 downto 0);
@@ -42,7 +40,7 @@ architecture top of calc is
        signal command : std_logic_vector(COMMAND_SIZE - 1 downto 0);
        signal command_data : std_logic_vector(3 * COLOR_SIZE + CHAR_SIZE -1 downto 0);
        -- history/display
-       signal d_new_eingabe, d_new_result : std_logic;
+       signal d_new_eingabe, d_new_result, d_new_bs : std_logic;
        signal d_zeile : hzeile;
        signal d_spalte : hspalte;
        signal d_get, d_done : std_logic;
@@ -53,18 +51,6 @@ architecture top of calc is
 
        -- tmp: history<>scanner
        signal do_it, finished : std_logic;
-
-       COMPONENT dcm_s3e
-       PORT(
-               CLKIN_IN : IN std_logic;
-               RST_IN : IN std_logic;
-               CLKIN_IBUFG_OUT : OUT std_logic;
-               CLK0_OUT : OUT std_logic;
-               CLK0_OUT1 : OUT std_logic;
-               LOCKED_OUT : OUT std_logic
-               );
-       END COMPONENT;
-
 begin
        led0 <= '0';
        led1 <= '1';
@@ -77,13 +63,13 @@ begin
                SYNC_STAGES => 2
        )
        port map (
-               sys_clk => sys_clk,
-               sys_res_n => sys_res_n,
+               sys_clk => CLK_50MHZ,
+               sys_res_n => '1',
                command => command,
                command_data => command_data,
                free => free,
                vga_clk => vga_clk,
-               vga_res_n => sys_res_n,
+               vga_res_n => '1',
                vsync_n => vsync_n,
                hsync_n => hsync_n,
                r => r,
@@ -92,23 +78,21 @@ begin
        );
 
        -- pll fuer vga
-       dcm_s3e_inst : dcm_s3e PORT MAP(
-               CLKIN_IN => sys_clk_real,
-               RST_IN => sys_res_n,
-               CLKIN_IBUFG_OUT => sys_clk,
-               CLK0_OUT => vga_clk,
-               CLK0_OUT1 => open,
-               LOCKED_OUT => open
+       clk_vga_s3e_inst : entity work.clk_vga_s3e(beh)
+       port map (
+               clk50 => CLK_50MHZ,
+               clk25 => vga_clk
        );
 
        -- display
        display_inst : entity work.display(beh)
        port map (
-               sys_clk => sys_clk,
-               sys_res_n => sys_res_n,
+               sys_clk => CLK_50MHZ,
+               sys_res_n => '1',
                -- history
                d_new_eingabe => d_new_eingabe,
                d_new_result => d_new_result,
+               d_new_bs => d_new_bs,
                d_zeile => d_zeile,
                d_spalte => d_spalte,
                d_get => d_get,
@@ -123,8 +107,8 @@ begin
        -- history
        history_inst : entity work.history(beh)
        port map (
-               sys_clk => sys_clk,
-               sys_res_n => sys_res_n,
+               sys_clk => CLK_50MHZ,
+               sys_res_n => '1',
                -- scanner
                s_char => s_char,
                s_take => s_take,
@@ -133,6 +117,7 @@ begin
                -- display
                d_new_eingabe => d_new_eingabe,
                d_new_result => d_new_result,
+               d_new_bs => d_new_bs,
                d_zeile => d_zeile,
                d_spalte => d_spalte,
                d_get => d_get,
@@ -146,8 +131,8 @@ begin
        -- scanner
        scanner_inst : entity work.scanner(beh)
        port map (
-               sys_clk => sys_clk,
-               sys_res_n => sys_res_n,
+               sys_clk => CLK_50MHZ,
+               sys_res_n => '1',
                -- ps/2
                new_data => new_data,
                data => data,
@@ -168,8 +153,8 @@ begin
                SYNC_STAGES => 2
        )
        port map (
-               sys_clk => sys_clk,
-               sys_res_n => sys_res_n,
+               sys_clk => CLK_50MHZ,
+               sys_res_n => '1',
                -- scanner
                new_data => new_data,
                data => data,