allgemein: components fuer die module

[hwmod.git] / src / calc_s3e.vhd

diff --git a/src/calc_s3e.vhd b/src/calc_s3e.vhd
index c43749d699d003a3243024e65159bc9dd5d3d3fc..3c67b22a9ddad56fc4ce1c6899c9da2e2156c2f0 100644 (file)
--- a/src/calc_s3e.vhd
+++ b/src/calc_s3e.vhd
@@ -6,15 +6,17 @@ use work.textmode_vga_component_pkg.all;
 use work.textmode_vga_pkg.all;
 use work.textmode_vga_platform_dependent_pkg.all;
 use work.ps2_keyboard_controller_pkg.all;
+use work.sync_pkg.all;
 
 entity calc is
        port (
                CLK_50MHZ : in std_logic;
                sys_res : in std_logic;
-               -- btnA
-               -- TODO: pins
+               -- btnA (here: "btn west")
+               btn_a : in std_logic;
                -- rs232
-               -- TODO: pins
+               rxd : in std_logic;
+               txd : out std_logic;
                -- vga
                vsync_n : out std_logic;
                hsync_n : out std_logic;
@@ -23,14 +25,13 @@ entity calc is
                b : out std_logic_vector(BLUE_BITS - 1 downto 0);
                -- ps/2
                ps2_clk : inout std_logic;
-               ps2_data : inout std_logic;
-               -- debug
-               led0 : out std_logic;
-               led1 : out std_logic
+               ps2_data : inout std_logic
        );
 end entity calc;
 
 architecture top of calc is
+       constant CLK_FREQ : integer := 50000000;
+       constant BAUDRATE : integer := 115200;
        -- reset
        signal sys_res_n : std_logic;
        -- ps/2
@@ -58,11 +59,20 @@ architecture top of calc is
        signal p_wdone : std_logic;
        signal p_write : hbyte;
        signal p_finished : std_logic;
+       --history/pc_com
+       signal pc_get : std_logic;
+       signal pc_spalte : hspalte;
+       signal pc_zeile : hzeile;
+       signal pc_char : hbyte;
+       signal pc_done : std_logic;
        -- parser/scanner
        signal do_it, finished : std_logic;
+       -- rs232
+       signal rx_new, rxd_sync : std_logic;
+       signal rx_data : std_logic_vector (7 downto 0);
+       signal tx_new, tx_done : std_logic;
+       signal tx_data : std_logic_vector (7 downto 0);
 begin
-       led0 <= '0';
-       led1 <= '1';
        sys_res_n <= not sys_res;
 
        -- vga/ipcore
@@ -140,7 +150,13 @@ begin
                p_wtake => p_wtake,
                p_wdone => p_wdone,
                p_write => p_write,
-               p_finished => p_finished
+               p_finished => p_finished,
+               -- pc communication
+               pc_get =>  pc_get,
+               pc_spalte => pc_spalte,
+               pc_zeile => pc_zeile,
+               pc_char => pc_char,
+               pc_done => pc_done
        );
 
        -- parser
@@ -182,7 +198,7 @@ begin
        -- ps/2
        ps2_inst : entity work.ps2_keyboard_controller(beh)
        generic map (
-               CLK_FREQ => 50000000,
+               CLK_FREQ => CLK_FREQ,
                SYNC_STAGES => 2
        )
        port map (
@@ -194,4 +210,68 @@ begin
                ps2_clk => ps2_clk,
                ps2_data => ps2_data
        );
+
+       -- synchronizer fuer rxd
+       sync_rxd_inst : entity work.sync(beh)
+       generic map (
+               SYNC_STAGES => 2,
+               RESET_VALUE => '1'
+       )
+       port map (
+               sys_clk => CLK_50MHZ,
+               sys_res_n => sys_res_n,
+               data_in => rxd,
+               data_out => rxd_sync
+       );
+
+       -- rs232-rx
+       rs232rx_inst : entity work.uart_rx(beh)
+       generic map (
+               CLK_FREQ => CLK_FREQ,
+               BAUDRATE => BAUDRATE
+       )
+       port map (
+               sys_clk => CLK_50MHZ,
+               sys_res_n => sys_res_n,
+               rxd => rxd_sync,
+               rx_data => rx_data,
+               rx_new => rx_new
+       );
+
+       -- rs232-tx
+       rs232tx_inst : entity work.uart_tx(beh)
+       generic map (
+               CLK_FREQ => CLK_FREQ,
+               BAUDRATE => BAUDRATE
+       )
+       port map (
+               sys_clk => CLK_50MHZ,
+               sys_res_n => sys_res_n,
+               txd => txd,
+               tx_data => tx_data,
+               tx_new => tx_new,
+               tx_done => tx_done
+       );
+
+       -- pc-com
+       pc_com_inst : entity work.pc_communication(beh)
+       port map (
+               sys_clk => CLK_50MHZ,
+               sys_res_n => sys_res_n,
+               --button
+               btn_a => not btn_a,
+               --uart_tx
+               tx_data => tx_data,
+               tx_new => tx_new,
+               tx_done => tx_done,
+               --uart_rx
+               rx_data => rx_data,
+               rx_new => rx_new,
+               -- History
+               pc_zeile => pc_zeile,
+               pc_spalte => pc_spalte,
+               pc_get => pc_get,
+               pc_done => pc_done,
+               pc_char => pc_char
+       );
 end architecture top;