spartan3e: pinmapping fuer uart

[hwmod.git] / src / calc_s3e.vhd

diff --git a/src/calc_s3e.vhd b/src/calc_s3e.vhd
index c43749d699d003a3243024e65159bc9dd5d3d3fc..040034ad3ec94bd49496f72f503241d0cd7d12b4 100644 (file)
--- a/src/calc_s3e.vhd
+++ b/src/calc_s3e.vhd
@@ -6,6 +6,7 @@ use work.textmode_vga_component_pkg.all;
 use work.textmode_vga_pkg.all;
 use work.textmode_vga_platform_dependent_pkg.all;
 use work.ps2_keyboard_controller_pkg.all;
+use work.sync_pkg.all;
 
 entity calc is
        port (
@@ -14,7 +15,8 @@ entity calc is
                -- btnA
                -- TODO: pins
                -- rs232
-               -- TODO: pins
+               rxd : in std_logic;
+               txd : out std_logic;
                -- vga
                vsync_n : out std_logic;
                hsync_n : out std_logic;
@@ -23,10 +25,7 @@ entity calc is
                b : out std_logic_vector(BLUE_BITS - 1 downto 0);
                -- ps/2
                ps2_clk : inout std_logic;
-               ps2_data : inout std_logic;
-               -- debug
-               led0 : out std_logic;
-               led1 : out std_logic
+               ps2_data : inout std_logic
        );
 end entity calc;
 
@@ -60,9 +59,12 @@ architecture top of calc is
        signal p_finished : std_logic;
        -- parser/scanner
        signal do_it, finished : std_logic;
+       -- rs232
+       signal rx_new, rxd_sync : std_logic;
+       signal rx_data : std_logic_vector (7 downto 0);
+       signal tx_new, tx_done : std_logic;
+       signal tx_data : std_logic_vector (7 downto 0);
 begin
-       led0 <= '0';
-       led1 <= '1';
        sys_res_n <= not sys_res;
 
        -- vga/ipcore
@@ -194,4 +196,46 @@ begin
                ps2_clk => ps2_clk,
                ps2_data => ps2_data
        );
+
+       -- synchronizer fuer rxd
+       sync_rxd_inst : entity work.sync(beh)
+       generic map (
+               SYNC_STAGES => 2,
+               RESET_VALUE => '1'
+       )
+       port map (
+               sys_clk => CLK_50MHZ,
+               sys_res_n => sys_res_n,
+               data_in => rxd,
+               data_out => rxd_sync
+       );
+
+       -- rs232-rx
+       rs232rx_inst : entity work.uart_rx(beh)
+       generic map (
+               CLK_FREQ => 50000000,
+               BAUDRATE => 115200
+       )
+       port map (
+               sys_clk => CLK_50MHZ,
+               sys_res_n => sys_res_n,
+               rxd => rxd_sync,
+               rx_data => rx_data,
+               rx_new => rx_new
+       );
+
+       -- rs232-tx
+       rs232tx_inst : entity work.uart_tx(beh)
+       generic map (
+               CLK_FREQ => 50000000,
+               BAUDRATE => 115200
+       )
+       port map (
+               sys_clk => CLK_50MHZ,
+               sys_res_n => sys_res_n,
+               txd => txd,
+               tx_data => tx_data,
+               tx_new => tx_new,
+               tx_done => tx_done
+       );
 end architecture top;