allgemein: components fuer die module

[hwmod.git] / src / calc.vhd

diff --git a/src/calc.vhd b/src/calc.vhd
index cdee994ba039e688a034856345e279613f82c02c..20d2027e62013e409327ac531a1f4792612e3207 100644 (file)
--- a/src/calc.vhd
+++ b/src/calc.vhd
@@ -14,9 +14,10 @@ entity calc is
                sys_clk : in std_logic;
                sys_res_n : in std_logic;
                -- btnA
-               -- TODO: pins
+               btn_a : in std_logic;
                -- rs232
-               -- TODO: pins
+               rxd : in std_logic;
+               txd : out std_logic;
                -- vga
                vsync_n : out std_logic;
                hsync_n : out std_logic;
@@ -30,6 +31,8 @@ entity calc is
 end entity calc;
 
 architecture top of calc is
+       constant CLK_FREQ : integer := 33000000;
+       constant BAUDRATE : integer := 115200;
        -- ps/2
        signal new_data : std_logic;
        signal data : std_logic_vector(7 downto 0);
@@ -55,13 +58,25 @@ architecture top of calc is
        signal p_wdone : std_logic;
        signal p_write : hbyte;
        signal p_finished : std_logic;
+       --history/pc_com
+       signal pc_get : std_logic;
+       signal pc_spalte : hspalte;
+       signal pc_zeile : hzeile;
+       signal pc_char : hbyte;
+       signal pc_done : std_logic;
        -- parser/scanner
        signal do_it, finished : std_logic;
        -- debouncing
        signal sys_res_n_sync : std_logic;
+       signal btn_a_sync : std_logic;
+       -- rs232
+       signal rx_new, rxd_sync : std_logic;
+       signal rx_data : std_logic_vector (7 downto 0);
+       signal tx_new, tx_done : std_logic;
+       signal tx_data : std_logic_vector (7 downto 0);
 begin
        -- vga/ipcore
-       textmode_vga_inst : entity work.textmode_vga(struct)
+       textmode_vga_inst : textmode_vga
        generic map (
                VGA_CLK_FREQ => 25000000,
                BLINK_INTERVAL_MS => 500,
@@ -83,14 +98,14 @@ begin
        );
 
        -- pll fuer vga
-       vpll_inst : entity work.vpll(syn)
+       vpll_inst : vpll
        port map (
                inclk0 => sys_clk,
                c0 => vga_clk
        );
 
        -- display
-       display_inst : entity work.display(beh)
+       display_inst : display
        port map (
                sys_clk => sys_clk,
                sys_res_n => sys_res_n_sync,
@@ -110,7 +125,7 @@ begin
        );
 
        -- history
-       history_inst : entity work.history(beh)
+       history_inst : history
        port map (
                sys_clk => sys_clk,
                sys_res_n => sys_res_n_sync,
@@ -135,11 +150,17 @@ begin
                p_wtake => p_wtake,
                p_wdone => p_wdone,
                p_write => p_write,
-               p_finished => p_finished
+               p_finished => p_finished,
+               -- pc communication
+               pc_get =>  pc_get,
+               pc_spalte => pc_spalte,
+               pc_zeile => pc_zeile,
+               pc_char => pc_char,
+               pc_done => pc_done
        );
 
        -- parser
-       parser_inst : entity work.parser(beh)
+       parser_inst : parser
        port map (
                sys_clk => sys_clk,
                sys_res_n => sys_res_n_sync,
@@ -157,7 +178,7 @@ begin
        );
 
        -- scanner
-       scanner_inst : entity work.scanner(beh)
+       scanner_inst : scanner
        port map (
                sys_clk => sys_clk,
                sys_res_n => sys_res_n_sync,
@@ -175,9 +196,9 @@ begin
        );
 
        -- ps/2
-       ps2_inst : entity work.ps2_keyboard_controller(beh)
+       ps2_inst : ps2_keyboard_controller
        generic map (
-               CLK_FREQ => 33330000,
+               CLK_FREQ => CLK_FREQ,
                SYNC_STAGES => 2
        )
        port map (
@@ -193,7 +214,7 @@ begin
        -- debouncer fuer sys_res_n
        sys_res_n_debounce_inst : debounce
        generic map (
-               CLK_FREQ => 33330000,
+               CLK_FREQ => CLK_FREQ,
                TIMEOUT => 1 ms,
                RESET_VALUE => '1',
                SYNC_STAGES => 2
@@ -204,5 +225,83 @@ begin
                data_in => sys_res_n,
                data_out => sys_res_n_sync
        );
-end architecture top;
 
+       -- synchronizer fuer rxd
+       sync_rxd_inst : sync
+       generic map (
+               SYNC_STAGES => 2,
+               RESET_VALUE => '1'
+       )
+       port map (
+               sys_clk => sys_clk,
+               sys_res_n => sys_res_n_sync,
+               data_in => rxd,
+               data_out => rxd_sync
+       );
+
+       -- debouncer fuer btn_a
+       btn_a_debounce_inst : debounce
+       generic map (
+               CLK_FREQ => CLK_FREQ,
+               TIMEOUT => 1 ms,
+               RESET_VALUE => '1',
+               SYNC_STAGES => 2
+       )
+       port map (
+               sys_clk => sys_clk,
+               sys_res_n => sys_res_n_sync,
+               data_in => btn_a,
+               data_out => btn_a_sync
+       );
+
+       -- rs232-rx
+       rs232rx_inst : uart_rx
+       generic map (
+               CLK_FREQ => CLK_FREQ,
+               BAUDRATE => BAUDRATE
+       )
+       port map (
+               sys_clk => sys_clk,
+               sys_res_n => sys_res_n_sync,
+               rxd => rxd_sync,
+               rx_data => rx_data,
+               rx_new => rx_new
+       );
+
+       -- rs232-tx
+       rs232tx_inst : uart_tx
+       generic map (
+               CLK_FREQ => CLK_FREQ,
+               BAUDRATE => BAUDRATE
+       )
+       port map (
+               sys_clk => sys_clk,
+               sys_res_n => sys_res_n,
+               txd => txd,
+               tx_data => tx_data,
+               tx_new => tx_new,
+               tx_done => tx_done
+       );
+
+       pc_com_inst : pc_communication
+       port map (
+               sys_clk => sys_clk,
+               sys_res_n => sys_res_n,
+               --button
+               btn_a => btn_a_sync,
+               --uart_tx
+               tx_data => tx_data,
+               tx_new => tx_new,
+               tx_done => tx_done,
+               --uart_rx
+               rx_data => rx_data,
+               rx_new => rx_new,
+               -- History
+               pc_zeile => pc_zeile,
+               pc_spalte => pc_spalte,
+               pc_get => pc_get,
+               pc_done => pc_done,
+               pc_char => pc_char
+       );
+
+end architecture top;