end entity calc;
architecture top of calc is
+ constant CLK_FREQ : integer := 33000000;
+ constant BAUDRATE : integer := 115200;
-- ps/2
signal new_data : std_logic;
signal data : std_logic_vector(7 downto 0);
signal do_it, finished : std_logic;
-- debouncing
signal sys_res_n_sync : std_logic;
+ signal btn_a_sync : std_logic;
-- rs232
signal rx_new, rxd_sync : std_logic;
signal rx_data : std_logic_vector (7 downto 0);
signal tx_new, tx_done : std_logic;
signal tx_data : std_logic_vector (7 downto 0);
-
- signal btn_a_sync : std_logic;
-
begin
-- vga/ipcore
- textmode_vga_inst : entity work.textmode_vga(struct)
+ textmode_vga_inst : textmode_vga
generic map (
VGA_CLK_FREQ => 25000000,
BLINK_INTERVAL_MS => 500,
);
-- pll fuer vga
- vpll_inst : entity work.vpll(syn)
+ vpll_inst : vpll
port map (
inclk0 => sys_clk,
c0 => vga_clk
);
-- display
- display_inst : entity work.display(beh)
+ display_inst : display
port map (
sys_clk => sys_clk,
sys_res_n => sys_res_n_sync,
);
-- history
- history_inst : entity work.history(beh)
+ history_inst : history
port map (
sys_clk => sys_clk,
sys_res_n => sys_res_n_sync,
pc_zeile => pc_zeile,
pc_char => pc_char,
pc_done => pc_done
-
);
-- parser
- parser_inst : entity work.parser(beh)
+ parser_inst : parser
port map (
sys_clk => sys_clk,
sys_res_n => sys_res_n_sync,
);
-- scanner
- scanner_inst : entity work.scanner(beh)
+ scanner_inst : scanner
port map (
sys_clk => sys_clk,
sys_res_n => sys_res_n_sync,
);
-- ps/2
- ps2_inst : entity work.ps2_keyboard_controller(beh)
+ ps2_inst : ps2_keyboard_controller
generic map (
- CLK_FREQ => 33330000,
+ CLK_FREQ => CLK_FREQ,
SYNC_STAGES => 2
)
port map (
-- debouncer fuer sys_res_n
sys_res_n_debounce_inst : debounce
generic map (
- CLK_FREQ => 33330000,
+ CLK_FREQ => CLK_FREQ,
TIMEOUT => 1 ms,
RESET_VALUE => '1',
SYNC_STAGES => 2
);
-- synchronizer fuer rxd
- sync_rxd_inst : entity work.sync(beh)
+ sync_rxd_inst : sync
generic map (
SYNC_STAGES => 2,
RESET_VALUE => '1'
-- debouncer fuer btn_a
btn_a_debounce_inst : debounce
generic map (
- CLK_FREQ => 33330000,
+ CLK_FREQ => CLK_FREQ,
TIMEOUT => 1 ms,
RESET_VALUE => '1',
SYNC_STAGES => 2
)
port map (
sys_clk => sys_clk,
- sys_res_n => '1',
+ sys_res_n => sys_res_n_sync,
data_in => btn_a,
data_out => btn_a_sync
);
-- rs232-rx
- rs232rx_inst : entity work.uart_rx(beh)
+ rs232rx_inst : uart_rx
generic map (
- CLK_FREQ => 33330000,
- BAUDRATE => 115200
+ CLK_FREQ => CLK_FREQ,
+ BAUDRATE => BAUDRATE
)
port map (
sys_clk => sys_clk,
);
-- rs232-tx
- rs232tx_inst : entity work.uart_tx(beh)
+ rs232tx_inst : uart_tx
generic map (
- CLK_FREQ => 33330000,
- BAUDRATE => 115200
+ CLK_FREQ => CLK_FREQ,
+ BAUDRATE => BAUDRATE
)
port map (
sys_clk => sys_clk,
tx_done => tx_done
);
- pc_com_inst : entity work.pc_communication(beh)
+ pc_com_inst : pc_communication
port map (
sys_clk => sys_clk,
sys_res_n => sys_res_n,
rx_data => rx_data,
rx_new => rx_new,
-- History
- d_zeile => pc_zeile,
- d_spalte => pc_spalte,
- d_get => pc_get,
- d_done => pc_done,
- d_char => pc_char
+ pc_zeile => pc_zeile,
+ pc_spalte => pc_spalte,
+ pc_get => pc_get,
+ pc_done => pc_done,
+ pc_char => pc_char
);
end architecture top;
-