uart_rx: ein prozessmodell. spart weitere 3 logic elements :P

[hwmod.git] / src / beh_scanner_tb.vhd

diff --git a/src/beh_scanner_tb.vhd b/src/beh_scanner_tb.vhd
index 795e4e86f38bffa0fafed35f36610d1a43ec68ec..d9b7bb4610d4942cf4ee31cca788896c29e9cdf3 100644 (file)
--- a/src/beh_scanner_tb.vhd
+++ b/src/beh_scanner_tb.vhd
@@ -21,7 +21,7 @@ architecture sim of beh_scanner_tb is
 
        signal stop : boolean := false;
 begin
-       inst : entity work.scanner(beh)
+       inst : scanner
        port map (
                sys_clk => sys_clk,
                sys_res_n => sys_res_n,