library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.gen_pkg.all; entity beh_scanner_tb is end entity beh_scanner_tb; architecture sim of beh_scanner_tb is -- system signal sys_clk, sys_res_n : std_logic; -- ps/2 signal new_data : std_logic; signal data : std_logic_vector(7 downto 0); -- history signal s_char : hbyte; signal s_take, s_done, s_backspace : std_logic; -- parser signal do_it : std_logic; signal finished : std_logic; signal stop : boolean := false; begin inst : scanner port map ( sys_clk => sys_clk, sys_res_n => sys_res_n, -- ps/2 new_data => new_data, data => data, -- history s_char => s_char, s_take => s_take, s_done => s_done, s_backspace => s_backspace, -- Parser do_it => do_it, finished => finished ); process begin sys_clk <= '0'; wait for 15 ns; sys_clk <= '1'; wait for 15 ns; if stop = true then wait; end if; end process; process -- textio stuff use std.textio.all; file f : text open read_mode is "../../src/scanner.test"; variable l : line; variable input : hstring; variable expectedresult : hstring; variable realresult : hstring; variable checkall : boolean := true; variable run_tc, run_inner : boolean := true; variable i, j, k, y : natural; begin -- init & reset sys_res_n <= '0'; new_data <= '0'; data <= (others => '0'); s_done <= '0'; finished <= '0'; icwait(sys_clk, 5); sys_res_n <= '1'; i := 1; f_loop : while not endfile(f) loop data <= (others => '0'); realresult := (others => nul); f1_loop : while not endfile(f) loop readline (f, l); input := (others => nul); if (l'length <= HSPALTE_MAX+1) then input(1 to l'length) := l.all; if (input(1) = '#') then next f1_loop; else exit f1_loop; end if; else report "fehler in scanner.test: eingabe zu lange in testfall " & natural'image(i); next f_loop; end if; end loop f1_loop; f2_loop : while not endfile(f) loop readline (f, l); expectedresult := (others => nul); if (l'length <= HSPALTE_MAX+1) then expectedresult(1 to l'length) := l.all; if (expectedresult(1) = '#') then next f2_loop; else y := l'length; exit f2_loop; end if; else report "fehler in scanner.test: eingabe zu lange in testfall " & natural'image(i); next f_loop; end if; end loop f2_loop; report "testcase(" & natural'image(i) & ").input: " & input; report "testcase(" & natural'image(i) & ").expectedresult: " & expectedresult; i := i + 1; icwait(sys_clk, 5); run_tc := true; j := 0; k := 1; mainl : while run_tc loop icwait(sys_clk, 1); j := j + 1; if j = 73 then run_tc := false; assert(false) report "wtf @ schleife"; next mainl; end if; new_data <= '1'; case input(j) is when nul => data <= ascii2sc(x"1c"); -- $ (enter) when '!' => data <= ascii2sc(x"0e"); -- ! (backspace) when '/' => data <= x"e0"; icwait(sys_clk, 1); new_data <= '0'; icwait(sys_clk, 1); new_data <= '1'; data <= SC_KP_DIV; when others => data <= ascii2sc(std_logic_vector(to_unsigned(character'pos(input(j)),8))); end case; icwait(sys_clk, 1); new_data <= '0'; -- ack'en skippen, falls es ein "spezielles" zeichen ist if(not valid_char(data)) then next mainl; end if; -- wuenschswert waere das hier: -- > wait on s_backspace, s_take, do_it; -- geht aber leider nicht, weil sich die signale vllt schon -- geaendert haben run_inner := true; main_inner : while run_inner loop icwait(sys_clk, 1); run_inner := false; if s_backspace = '1' then if k > 1 then realresult(k) := nul; k := k - 1; realresult(k) := nul; end if; icwait(sys_clk, 1); s_done <= '1'; wait on s_take; -- = '0' icwait(sys_clk, 1); s_done <= '0'; elsif do_it = '1' then -- dauert normalweiser noch laenger (parser braucht -- relativ lange) icwait(sys_clk, 7); finished <= '1'; wait on do_it; -- = '0' icwait(sys_clk, 1); finished <= '0'; run_tc := false; elsif s_take = '1' then realresult(k) := character'val(to_integer(unsigned(s_char))); k := k + 1; icwait(sys_clk, 1); s_done <= '1'; wait on s_take; -- = '0' icwait(sys_clk, 1); s_done <= '0'; else -- assert(false) report "scanner_tb: kann passieren. wenn tb haengt, dann hier auskommentieren"; run_inner := true; end if; end loop; end loop; report "realresult : " & realresult; if realresult /= expectedresult then checkall := false; end if; report "=================="; end loop f_loop; if checkall then report "alle testfaelle des Scanners waren erfolgreich!"; else report "nicht alle testfaelle des Scanners waren erfolgreich!"; end if; stop <= true; wait; end process; end architecture sim;