uart_rx: ein prozessmodell. spart weitere 3 logic elements :P

[hwmod.git] / src / beh_scanner_tb.vhd

diff --git a/src/beh_scanner_tb.vhd b/src/beh_scanner_tb.vhd
index 342b1c53752723fe197f1b8372d15ff07c2524d4..d9b7bb4610d4942cf4ee31cca788896c29e9cdf3 100644 (file)
--- a/src/beh_scanner_tb.vhd
+++ b/src/beh_scanner_tb.vhd
@@ -21,7 +21,7 @@ architecture sim of beh_scanner_tb is
 
        signal stop : boolean := false;
 begin
-       inst : entity work.scanner(beh)
+       inst : scanner
        port map (
                sys_clk => sys_clk,
                sys_res_n => sys_res_n,
@@ -50,48 +50,6 @@ begin
        end process;
 
        process
-               function ascii2sc (x : hbyte) return hbyte is
-                       variable y : hbyte;
-               begin
-                       case x is
-                               when x"30" => y := SC_KP_0;
-                               when x"31" => y := SC_KP_1;
-                               when x"32" => y := SC_KP_2;
-                               when x"33" => y := SC_KP_3;
-                               when x"34" => y := SC_KP_4;
-                               when x"35" => y := SC_KP_5;
-                               when x"36" => y := SC_KP_6;
-                               when x"37" => y := SC_KP_7;
-                               when x"38" => y := SC_KP_8;
-                               when x"39" => y := SC_KP_9;
-                               when x"2b" => y := SC_KP_PLUS;
-                               when x"2d" => y := SC_KP_MINUS;
-                               when x"2a" => y := SC_KP_MUL;
-                               when x"2f" => y := SC_KP_DIV;
-                               when x"20" => y := SC_SPACE;
-                               when x"1c" => y := SC_ENTER;
-                               when x"0e" => y := SC_BKSP;
-                               when others => y := x"41";
-                       end case;
-                       return y;
-               end function;
-
-               function valid_char (x : std_logic_vector(7 downto 0)) return boolean is
-                               variable y : boolean;
-               begin
-                       case x is
-                               when SC_KP_0 | SC_KP_1 | SC_KP_2 | SC_KP_3 |
-                                       SC_KP_4 | SC_KP_5 | SC_KP_6 | SC_KP_7 |
-                                       SC_KP_8 | SC_KP_9 | SC_KP_PLUS |
-                                       SC_KP_MINUS | SC_KP_MUL |
-                                       SC_KP_DIV | SC_SPACE |
-                                       SC_BKSP | SC_ENTER =>
-                                               y := true;
-                               when others => y := false;
-                       end case;
-                       return y;
-               end function;
-
                -- textio stuff
                use std.textio.all;
                file f : text open read_mode is "../../src/scanner.test";
@@ -123,7 +81,7 @@ begin
                        f1_loop : while not endfile(f) loop
                                readline (f, l);
                                input := (others => nul);
-                               if (l'length <= 72) then
+                               if (l'length <= HSPALTE_MAX+1) then
                                        input(1 to l'length) := l.all;
                                        if (input(1) = '#') then
                                                next f1_loop;
@@ -139,7 +97,7 @@ begin
                        f2_loop : while not endfile(f) loop
                                readline (f, l);
                                expectedresult := (others => nul);
-                               if (l'length <= 72) then
+                               if (l'length <= HSPALTE_MAX+1) then
                                        expectedresult(1 to l'length) := l.all;
                                        if (expectedresult(1) = '#') then
                                                next f2_loop;