beautify

[hwmod.git] / src / beh_pc_communication_tb.vhd

diff --git a/src/beh_pc_communication_tb.vhd b/src/beh_pc_communication_tb.vhd
index 03d1d62cac108c8c6663047136bc9fb56a53b20a..ae8ed744aa2ddf41cf7241f8169ff21a12f80c15 100644 (file)
--- a/src/beh_pc_communication_tb.vhd
+++ b/src/beh_pc_communication_tb.vhd
@@ -21,13 +21,13 @@ architecture sim of beh_pc_communication_tb is
                signal tx_new : std_logic;
                signal tx_done : std_logic;
                signal rx_new : std_logic;
-               signal d_get : std_logic;
-               signal d_done : std_logic;
+               signal pc_get : std_logic;
+               signal pc_done : std_logic;
                signal rx_data, tx_data : std_logic_vector(7 downto 0);
 
-               signal d_zeile : hzeile;
-               signal d_spalte : hspalte;
-               signal d_char : hbyte;
+               signal pc_zeile : hzeile;
+               signal pc_spalte : hspalte;
+               signal pc_char : hbyte;
 begin
        -- pc_communication
        inst : entity work.pc_communication(beh)
@@ -48,11 +48,11 @@ begin
                rx_new => rx_new,
 
                -- History
-               d_zeile => d_zeile,
-               d_spalte => d_spalte,
-               d_get => d_get,
-               d_done => d_done,
-               d_char => d_char
+               pc_zeile => pc_zeile,
+               pc_spalte => pc_spalte,
+               pc_get => pc_get,
+               pc_done => pc_done,
+               pc_char => pc_char
        );
 
        clk : process
@@ -73,8 +73,8 @@ begin
                variable l : line;
        begin
                --take control of the situation.
-               d_char <= (others => '0');
-               d_done <= '0';
+               pc_char <= (others => '0');
+               pc_done <= '0';
                wait until sys_res_n = '1';
 
                while not endfile (f) loop
@@ -82,14 +82,14 @@ begin
                        buf := l.all;
                        i := 1;
                        while i < l'length loop
-                               d_done <= '0';
-                               wait until rising_edge(d_get);
-                               d_char <= (others => '0');
+                               pc_done <= '0';
+                               wait until rising_edge(pc_get);
+                               pc_char <= (others => '0');
                                wait for 300 ns;
 
-                               d_char <= hbyte(std_logic_vector(to_unsigned(character'pos(buf(i)),8)));
+                               pc_char <= hbyte(std_logic_vector(to_unsigned(character'pos(buf(i)),8)));
                                i := i + 1;
-                               d_done <= '1';
+                               pc_done <= '1';
                                wait for 30 ns;
                                
                        end loop;