signal p_rw, p_rget, p_rdone, p_wtake, p_wdone, p_finished : std_logic;
signal p_read, p_write : hbyte;
signal p_spalte : hspalte;
-
- -- alu
- signal opcode : alu_ops;
- signal op1, op2, op3, opM : csigned;
- signal do_calc, calc_done, calc_error : std_logic;
-
--scanner
signal do_it : std_logic;
signal finished : std_logic;
p_wdone => p_wdone,
p_write => p_write,
p_finished => p_finished,
- -- ALU
- opcode => opcode,
- op1 => op1,
- op2 => op2,
- op3 => op3,
- opM => opM,
- do_calc => do_calc,
- calc_done => calc_done,
- calc_error => calc_error,
- -- TODO: calc_error : in std_logic;
-- Scanner
do_it => do_it,
finished => finished
);
- instalu : entity work.alu(beh)
- port map
- (
- sys_clk => sys_clk,
- sys_res_n => sys_res_n,
- do_calc => do_calc,
- calc_done => calc_done,
- calc_error => calc_error,
- op1 => op1,
- op2 => op2,
- op3 => op3,
- opM => opM,
- opcode => opcode
- );
-
process
begin
sys_clk <= '0';