uart_rx: ein prozessmodell. spart weitere 3 logic elements :P
[hwmod.git] / quartus / project_gen.tcl
index f8846a4e53bae87d086f1d1dfbe178fc367a507f..d608f1095ae2c18d53d6627aac33711d9748fcfa 100644 (file)
@@ -45,9 +45,13 @@ if {$make_assignments} {
        set_global_assignment -name VHDL_FILE ../../src/parser.vhd
        set_global_assignment -name VHDL_FILE ../../src/scanner.vhd
        set_global_assignment -name VHDL_FILE ../../src/display.vhd
+       set_global_assignment -name VHDL_FILE ../../src/sp_ram.vhd
        set_global_assignment -name VHDL_FILE ../../src/history.vhd
        set_global_assignment -name VHDL_FILE ../../src/calc.vhd
        set_global_assignment -name VHDL_FILE ../../src/vpll.vhd
+       set_global_assignment -name VHDL_FILE ../../src/uart_tx.vhd
+       set_global_assignment -name VHDL_FILE ../../src/uart_rx.vhd
+       set_global_assignment -name VHDL_FILE ../../src/pc_communication.vhd
        
        #vga ip-core
        set_global_assignment -name VHDL_FILE ../../src/textmode_vga/console_sm.vhd
@@ -82,6 +86,20 @@ if {$make_assignments} {
        #gen ip-core
        set_global_assignment -name VHDL_FILE ../../src/math_pkg.vhd
 
+       #debouncing
+       set_global_assignment -name VHDL_FILE ../../src/debouncing/counter.vhd
+       set_global_assignment -name VHDL_FILE ../../src/debouncing/counter_beh.vhd
+       set_global_assignment -name VHDL_FILE ../../src/debouncing/debounce.vhd
+       set_global_assignment -name VHDL_FILE ../../src/debouncing/debounce_fsm.vhd
+       set_global_assignment -name VHDL_FILE ../../src/debouncing/debounce_fsm_beh.vhd
+       set_global_assignment -name VHDL_FILE ../../src/debouncing/debounce_pkg.vhd
+       set_global_assignment -name VHDL_FILE ../../src/debouncing/debounce_struct.vhd
+       set_global_assignment -name VHDL_FILE ../../src/debouncing/event_counter.vhd
+       set_global_assignment -name VHDL_FILE ../../src/debouncing/event_counter_beh.vhd
+       set_global_assignment -name VHDL_FILE ../../src/debouncing/event_counter_pkg.vhd
+       set_global_assignment -name VHDL_FILE ../../src/debouncing/sync.vhd
+       set_global_assignment -name VHDL_FILE ../../src/debouncing/sync_beh.vhd
+       set_global_assignment -name VHDL_FILE ../../src/debouncing/sync_pkg.vhd
 
        #pin mapping/system
        set_location_assignment PIN_N3 -to sys_clk
@@ -90,21 +108,30 @@ if {$make_assignments} {
        #vga
        set_location_assignment PIN_F1 -to hsync_n
        set_location_assignment PIN_F2 -to vsync_n
-       set_location_assignment E22 -to r[0]
-       set_location_assignment T4 -to r[1]
-       set_location_assignment T7 -to r[2]
-       set_location_assignment E23 -to g[0]
-       set_location_assignment T5 -to g[1]
-       set_location_assignment T24 -to g[2]
-       set_location_assignment E24 -to b[0]
-       set_location_assignment T6 -to b[1]
+       set_location_assignment PIN_E22 -to r[0]
+       set_location_assignment PIN_T4 -to r[1]
+       set_location_assignment PIN_T7 -to r[2]
+       set_location_assignment PIN_E23 -to g[0]
+       set_location_assignment PIN_T5 -to g[1]
+       set_location_assignment PIN_T24 -to g[2]
+       set_location_assignment PIN_E24 -to b[0]
+       set_location_assignment PIN_T6 -to b[1]
 
        #ps/2
-       set_location_assignment Y26 -to ps2_clk
-       set_location_assignment E21 -to ps2_data
+       set_location_assignment PIN_Y26 -to ps2_clk
+       set_location_assignment PIN_E21 -to ps2_data
+
+       #rs232
+       set_location_assignment PIN_D22 -to txd
+       set_location_assignment PIN_D23 -to rxd
+
+       #btn_a
+       set_location_assignment PIN_A3 -to btn_a
 
        set_global_assignment -name FMAX_REQUIREMENT "33.33 MHz" -section_id sys_clk
        set_instance_assignment -name CLOCK_SETTINGS sys_clk -to sys_clk
+       #warning fix fuer pll
+       set_global_assignment -name ENABLE_CLOCK_LATENCY ON
 
        set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
        set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"