2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4 --use work.gen_pkg.all;
7 -- type STATE_UART_TX is (IDLE, STARTBITS, PAYLOAD, PARITY, STOP, DONE);
8 -- type PARITY_TYPE is (ODD, EVEN, NONE);
9 --end package int_types;
13 CLK_FREQ : integer := 33000000;
14 BAUDRATE : integer := 115200
17 sys_clk : in std_logic;
18 sys_res_n : in std_logic;
20 tx_data : in std_logic_vector(7 downto 0);
21 tx_new : in std_logic;
22 tx_done : out std_logic
26 architecture beh of uart_tx is
27 constant BAUD : integer := CLK_FREQ/BAUDRATE;
29 type STATE_UART_TX is (IDLE, SENDBITS, DONE);
30 signal state_int, state_next : STATE_UART_TX;
32 signal txd_next, txd_int : std_logic;
33 signal tx_done_next, tx_done_int : std_logic;
34 signal tx_to_send : std_logic_vector(0 to 10);
35 signal bitcnt_int, bitcnt_next : integer range 0 to 10;
36 signal baudcnt_int, baudcnt_next : integer range 0 to BAUD;
39 tx_done <= tx_done_int;
41 process (sys_clk, sys_res_n)
43 if sys_res_n = '0' then
49 tx_to_send <= (others => '0');
50 elsif rising_edge(sys_clk) then
51 state_int <= state_next;
53 tx_done_int <= tx_done_next;
54 bitcnt_int <= bitcnt_next;
55 baudcnt_int <= baudcnt_next;
56 -- HIGHBIT (1) | STARTBIT (1) | DATA (8) | STOPBIT (1)
57 -- TODO: passt das wegen der endianess?
58 tx_to_send <= '1' & '0' & tx_data & '1';
62 process(tx_new, tx_to_send, state_int, bitcnt_int, baudcnt_int)
64 state_next <= state_int;
65 tx_done_next <= tx_done_int;
67 bitcnt_next <= bitcnt_int;
68 baudcnt_next <= baudcnt_int;
75 -- das highbyte sofort anlegen
78 state_next <= SENDBITS;
81 if bitcnt_int <= 10 then
82 if baudcnt_int < BAUD then
83 baudcnt_next <= baudcnt_int + 1;
85 txd_next <= tx_to_send(bitcnt_int);
86 bitcnt_next <= bitcnt_int + 1;
90 -- fuer das stopbit auch noch warten
91 if baudcnt_int < BAUD then
92 baudcnt_next <= baudcnt_int + 1;
104 end architecture beh;