2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
8 sys_clk : in std_logic;
9 sys_res : in std_logic;
10 txd : in std_logic; -- warning: this is asynchronous input!
11 tx_data : out std_logic_vector(7 downto 0); -- map this to a larger register with containing input
12 tx_new : out std_logic
16 architecture beh of uart_rx is
17 constant timer_max : integer := 35;
18 constant counter_max : integer := 9;
19 constant samples : integer := 8;
21 type STATE_UART_RX is (IDLE, BUSY, DONE);
23 signal timer, timer_next : integer range 0 to 65535;
24 signal counter, counter_next : integer range 0 to 15;
25 signal sample_counter, sample_counter_next : integer range 0 to counter_max-1;
26 signal state, state_next : STATE_UART_RX;
27 signal sync1, sync2, txd_next: std_logic; --synchronizers FIXME!
29 -- these are internal signals that are actually used as in and output
30 signal tx_data_prev : std_logic_vector(7 downto 0);
31 signal tx_new_i : std_logic;
32 signal shift, shift_value, shift_reset : std_logic;
37 process(sys_clk, sys_res)
39 if (sys_res = '0') then
42 tx_data_prev <= X"00";
44 txd_next <= '0'; --fixme: syncronizers!
49 elsif rising_edge(sys_clk) then
53 tx_data(7 downto 1) <= tx_data_prev(6 downto 1);
54 tx_data(0) <= shift_value;
55 elsif ( shift_reset = '1') then
59 txd_next <= sync2; --fixme: syncronizers!
62 counter <= counter_next;
63 sample_counter <= sample_counter_next;
68 process(state, txd, counter)
85 if (counter = counter_max) then --FIXME: is this true?
89 if (timer = timer_max) then
91 counter_next <= counter + 1;
92 if (sample_counter < samples/2) then
99 timer_next <= timer + 1;
102 if timer = timer_max/samples and txd_next = '1' then
103 sample_counter_next <= sample_counter + 1;
110 end architecture beh;