src/textmode_vga/console_sm_sync_beh.vhd

   1 -------------------------------------------------------------------------\r
   2 --\r
   3 -- Filename: console_sm_sync_beh.vhd\r
   4 -- =========\r
   5 --\r
   6 -- Short Description:\r
   7 -- ==================\r
   8 --   Behavioral implementation of the synchronizer for the cosole mode\r
   9 --   finite state machine. It synchronizes all signal crossing\r
  10 --   from the system and the VGA clock domain and vice versa.\r
  11 --\r
  12 -------------------------------------------------------------------------\r
  13 \r
  14 library ieee;
  15 use ieee.std_logic_1164.all;
  16 use ieee.numeric_std.all;
  17 use work.textmode_vga_pkg.all;
  18 use work.textmode_vga_platform_dependent_pkg.all;
  19 use work.font_pkg.all;
  20
  21 architecture beh of console_sm_sync is
  22   type SYNC_STATE_TYPE is (STATE_IDLE, STATE_WAIT_ACK, STATE_FINISHED, STATE_WAIT_ACK_RELEASE);
  23   signal sync_state, sync_state_next : SYNC_STATE_TYPE;
  24   signal command_req_sync : std_logic_vector(0 to SYNC_STAGES - 1);
  25   signal command_req_sys : std_logic;
  26   signal ack_sync : std_logic_vector(0 to SYNC_STAGES - 1);
  27   signal ack_sys : std_logic;
  28   signal command_latched, command_latched_next : std_logic_vector(COMMAND_SIZE - 1 downto 0);
  29   signal command_data_latched, command_data_latched_next : std_logic_vector(3 * COLOR_SIZE + CHAR_SIZE - 1 downto 0);
  30   signal command_req_next : std_logic;
  31 begin
  32   command_vga <= command_latched;
  33   command_data_vga <= command_data_latched;
  34   command_req_vga <= command_req_sync(SYNC_STAGES - 1);
  35   synchronizer_sys_vga : process(vga_clk, vga_res_n)
  36   begin
  37     if vga_res_n = '0' then
  38       command_req_sync <= (others => '0');
  39     elsif rising_edge(vga_clk) then
  40       command_req_sync(0) <= command_req_sys;
  41       for i in 1 to SYNC_STAGES - 1 loop
  42         command_req_sync(i) <= command_req_sync(i - 1);
  43       end loop;
  44     end if;
  45   end process synchronizer_sys_vga;
  46
  47   ack_sys <= ack_sync(SYNC_STAGES - 1);
  48   synchronizer_vga_sys : process(sys_clk, sys_res_n)
  49   begin
  50     if sys_res_n = '0' then
  51       ack_sync <= (others => '0');
  52     elsif rising_edge(sys_clk) then
  53       ack_sync(0) <= ack_vga;
  54       for i in 1 to SYNC_STAGES - 1 loop
  55         ack_sync(i) <= ack_sync(i - 1);
  56       end loop;
  57     end if;
  58   end process synchronizer_vga_sys;
  59
  60   process(sync_state, command_sys, ack_sys)
  61   begin
  62     sync_state_next <= sync_state;
  63
  64     case sync_state is
  65       when STATE_IDLE =>
  66         if command_sys /= COMMAND_NOP then
  67           if ack_sys = '0' then
  68             sync_state_next <= STATE_WAIT_ACK;
  69           else
  70             sync_state_next <= STATE_WAIT_ACK_RELEASE;
  71           end if;
  72         end if;
  73       when STATE_WAIT_ACK =>
  74         if ack_sys = '1' then
  75           sync_state_next <= STATE_FINISHED;
  76         end if;
  77       when STATE_FINISHED =>
  78         sync_state_next <= STATE_IDLE;
  79       when STATE_WAIT_ACK_RELEASE =>
  80         if ack_sys = '0' then
  81           sync_state_next <= STATE_WAIT_ACK;
  82         end if;
  83     end case;
  84   end process;
  85
  86   process(sync_state, command_latched, command_data_latched, command_sys, command_data_sys)
  87   begin
  88     command_latched_next <= command_latched;
  89     command_data_latched_next <= command_data_latched;
  90     command_req_next <= '0';
  91     free_sys <= '0';
  92
  93     case sync_state is
  94       when STATE_IDLE =>
  95         command_latched_next <= command_sys;
  96         command_data_latched_next <= command_data_sys;\r
  97         free_sys <= '1';
  98       when STATE_WAIT_ACK =>
  99         command_req_next <= '1';
 100       when STATE_FINISHED =>
 101         null;
 102       when STATE_WAIT_ACK_RELEASE =>
 103         null;
 104     end case;
 105   end process;
 106
 107   process(sys_clk, sys_res_n)
 108   begin
 109     if sys_res_n = '0' then
 110       command_latched <= COMMAND_NOP;
 111       command_data_latched <= COLOR_BLACK & CHAR_NULL;
 112       sync_state <= STATE_IDLE;
 113       command_req_sys <= '0';
 114     elsif rising_edge(sys_clk) then
 115       command_latched <= command_latched_next;
 116       command_data_latched <= command_data_latched_next;
 117       sync_state <= sync_state_next;
 118       command_req_sys <= command_req_next;
 119     end if;
 120   end process;
 121 end architecture beh;