2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
6 -- "synchronous single port RAM
9 ADDR_WIDTH : integer range 1 to integer'high
12 sys_clk : in std_logic;
13 address : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
20 architecture beh of sp_ram is
21 subtype RAM_ENTRY_TYPE is hbyte;
22 type RAM_TYPE is array (0 to (2 ** ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
23 signal ram : RAM_TYPE := (others => x"00");
27 if rising_edge(sys_clk) then
28 data_out <= ram(to_integer(unsigned(address)));
30 ram(to_integer(unsigned(address))) <= data_in;