2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
6 entity post_scanner_tb is
7 end entity post_scanner_tb;
9 architecture sim of post_scanner_tb is
12 sys_clk : in std_logic;
13 sys_res_n : in std_logic;
15 new_data : in std_logic;
16 data : in std_logic_vector(7 downto 0);
19 s_take : out std_logic;
20 s_done : in std_logic;
21 s_backspace : out std_logic;
23 do_it : out std_logic;
24 finished : in std_logic
26 end component scanner;
28 signal sys_clk, sys_res_n : std_logic;
30 signal new_data : std_logic;
31 signal data : std_logic_vector(7 downto 0);
33 signal s_char : hbyte;
34 signal s_take, s_done, s_backspace : std_logic;
36 signal do_it : std_logic;
37 signal finished : std_logic;
39 signal stop : boolean := false;
44 sys_res_n => sys_res_n,
52 s_backspace => s_backspace,
70 function ascii2sc (x : hbyte) return hbyte is
74 when x"30" => y := SC_KP_0;
75 when x"31" => y := SC_KP_1;
76 when x"32" => y := SC_KP_2;
77 when x"33" => y := SC_KP_3;
78 when x"34" => y := SC_KP_4;
79 when x"35" => y := SC_KP_5;
80 when x"36" => y := SC_KP_6;
81 when x"37" => y := SC_KP_7;
82 when x"38" => y := SC_KP_8;
83 when x"39" => y := SC_KP_9;
84 when x"2b" => y := SC_KP_PLUS;
85 when x"2d" => y := SC_KP_MINUS;
86 when x"2a" => y := SC_KP_MUL;
87 when x"2f" => y := SC_KP_DIV;
88 when x"20" => y := SC_SPACE;
89 when x"1c" => y := SC_ENTER;
90 when x"0e" => y := SC_BKSP;
91 when others => y := x"41";
96 function valid_char (x : std_logic_vector(7 downto 0)) return boolean is
100 when SC_KP_0 | SC_KP_1 | SC_KP_2 | SC_KP_3 |
101 SC_KP_4 | SC_KP_5 | SC_KP_6 | SC_KP_7 |
102 SC_KP_8 | SC_KP_9 | SC_KP_PLUS |
103 SC_KP_MINUS | SC_KP_MUL |
104 SC_KP_DIV | SC_SPACE |
105 SC_BKSP | SC_ENTER =>
107 when others => y := false;
114 file f : text open read_mode is "../../src/scanner.test";
117 variable input : hstring;
118 variable expectedresult : hstring;
119 variable realresult : hstring;
121 variable checkall : boolean := true;
122 variable run_tc, run_inner : boolean := true;
123 variable i, j, k, y : natural;
128 data <= (others => '0');
136 f_loop : while not endfile(f) loop
137 data <= (others => '0');
138 realresult := (others => nul);
140 f1_loop : while not endfile(f) loop
142 input := (others => nul);
143 if (l'length <= HSPALTE_MAX+1) then
144 input(1 to l'length) := l.all;
145 if (input(1) = '#') then
151 report "fehler in scanner.test: eingabe zu lange in testfall " & natural'image(i);
156 f2_loop : while not endfile(f) loop
158 expectedresult := (others => nul);
159 if (l'length <= HSPALTE_MAX+1) then
160 expectedresult(1 to l'length) := l.all;
161 if (expectedresult(1) = '#') then
168 report "fehler in scanner.test: eingabe zu lange in testfall " & natural'image(i);
175 report "testcase(" & natural'image(i) & ").input: " & input;
176 report "testcase(" & natural'image(i) & ").expectedresult: " & expectedresult;
183 mainl : while run_tc loop
189 assert(false) report "wtf @ schleife";
196 when nul => data <= ascii2sc(x"1c"); -- $ (enter)
197 when '!' => data <= ascii2sc(x"0e"); -- ! (backspace)
205 when others => data <= ascii2sc(std_logic_vector(to_unsigned(character'pos(input(j)),8)));
210 -- ack'en skippen, falls es ein "spezielles" zeichen ist
211 if(not valid_char(data)) then
215 -- wuenschswert waere das hier:
216 -- > wait on s_backspace, s_take, do_it;
217 -- geht aber leider nicht, weil sich die signale vllt schon
220 main_inner : while run_inner loop
224 if s_backspace = '1' then
226 realresult(k) := nul;
228 realresult(k) := nul;
232 wait on s_take; -- = '0'
235 elsif do_it = '1' then
236 -- dauert normalweiser noch laenger (parser braucht
240 wait on do_it; -- = '0'
245 elsif s_take = '1' then
246 realresult(k) := character'val(to_integer(unsigned(s_char)));
251 wait on s_take; -- = '0'
255 -- assert(false) report "scanner_tb: kann passieren. wenn tb haengt, dann hier auskommentieren";
261 report "realresult : " & realresult;
262 if realresult /= expectedresult then
265 report "==================";
269 report "alle testfaelle des Scanners waren erfolgreich!";
271 report "nicht alle testfaelle des Scanners waren erfolgreich!";
276 end architecture sim;