2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
7 end entity post_alu_tb;
9 architecture sim of post_alu_tb is
10 -- TODO: braucht man hier wirklich eine andere entity definition?
14 sys_clk : in std_logic;
15 sys_res_n : in std_logic;
17 op1 : in std_logic_vector(31 downto 0);
18 op2 : in std_logic_vector(31 downto 0);
19 op3 : out std_logic_vector(31 downto 0);
20 opM : out std_logic_vector(31 downto 0);
21 do_calc : in std_logic;
22 calc_done : out std_logic;
23 calc_error : out std_logic
27 signal sys_clk, sys_res_n, do_calc, calc_done, calc_error : std_logic;
28 signal opcode : alu_ops;
29 signal op1, op2, op3, opM : std_logic_vector((CBITS-1) downto 0);
30 signal stop : boolean := false;
36 sys_res_n => sys_res_n,
38 calc_done => calc_done,
44 calc_error => calc_error
59 type alu_testv is record
68 -- ggf. groesse des arrays erhoehen
69 type alu_testv_array is array (natural range 0 to 65) of alu_testv;
71 variable testmatrix : alu_testv_array :=
72 ( 0 => (-5, ALU_DIV, 3, 2, -1, false),
73 1 => (7, ALU_ADD, 3, 0, 10, false),
74 2 => (7, ALU_SUB, 1, 0, 6, false),
75 3 => (7, ALU_DIV, 1, 0, 7, false),
76 4 => (7, ALU_DIV, 3, 1, 2, false),
77 5 => (7, ALU_ADD, 1, 0, 8, false),
78 6 => (7, ALU_MUL, 3, 0, 21, false),
79 7 => (-7, ALU_MUL, 3, 0, -21, false),
80 8 => (268435456, ALU_MUL, -2, 0, -536870912, false),
81 9 => (268435456, ALU_MUL, 2**5, 0, 0, false), -- um fuenf nach links shiften
82 10 => (268435456 + 5, ALU_MUL, 2**5, 0, 160, false), -- = 5 * (2^5)
83 11 => (100, ALU_DIV, 10, 0, 10, false),
84 12 => (100, ALU_DIV, 51, 49, 1, false),
85 13 => (100, ALU_DIV, 49, 2, 2, false),
86 14 => (153156, ALU_DIV, 3543, 807, 43, false),
87 15 => (-153156, ALU_DIV, 3543, 807, -43, false),
88 16 => (153156, ALU_DIV, -3543, 807, -43, false),
89 17 => (-153156, ALU_DIV, -3543, 807, 43, false),
90 -- add: sign and under-/overflow check
91 18 => (2147483647, ALU_ADD, -1, 0, 2147483646, false),
92 19 => (2147483647, ALU_ADD, 1, 0, 0, true),
93 20 => (-2147483645, ALU_ADD, -100, 0, 0, true),
94 21 => (7, ALU_ADD, 1, 0, 8, false),
95 22 => (7, ALU_ADD, -1, 0, 6, false),
96 23 => (-7, ALU_ADD, 1, 0, -6, false),
97 24 => (-7, ALU_ADD, -1, 0, -8, false),
98 -- sub: sign and under-/overflow check
99 25 => (-7, ALU_SUB, 1, 0, -8, false),
100 26 => (-7, ALU_SUB, -1, 0, -6, false),
101 27 => (7, ALU_SUB, 1, 0, 6, false),
102 28 => (7, ALU_SUB, -1, 0, 8, false),
103 29 => (-2147483645, ALU_SUB, 1000, 0, 0, true),
104 30 => (2147483645, ALU_SUB, -1000, 0, 0, true),
105 31 => (-1000, ALU_SUB, 2147483645, 0, 0, true),
106 32 => (1000, ALU_SUB, -2147483645, 0, 0, true),
107 -- mul: sign and under-/overflow check
108 33 => (3, ALU_MUL, 2, 0, 6, false),
109 34 => (3, ALU_MUL, -2, 0, -6, false),
110 35 => (-3, ALU_MUL, 2, 0, -6, false),
111 36 => (-3, ALU_MUL, -2, 0, 6, false),
112 37 => (90000, ALU_MUL, 100000, 0, 0, true),
113 38 => (90000, ALU_MUL, -100000, 0, 0, true),
114 39 => (-90000, ALU_MUL, 100000, 0, 0, true),
115 40 => (-90000, ALU_MUL, -100000, 0, 0, true),
116 -- div: overflow check und division durch null
117 41 => (-2147483648, ALU_DIV, -1, 0, 0, true),
118 42 => (-2147483648, ALU_DIV, 0, 0, 0, true),
119 43 => (-4, ALU_DIV, 2, 0, -2, false),
121 44 => (1234, ALU_DIV, 3, 1, 411, false),
122 45 => (1, ALU_DIV, 10, 1, 0, false),
123 46 => (2, ALU_DIV, 10, 2, 0, false),
124 47 => (3, ALU_DIV, 10, 3, 0, false),
125 48 => (4, ALU_DIV, 10, 4, 0, false),
126 49 => (5, ALU_DIV, 10, 5, 0, false),
127 50 => (6, ALU_DIV, 10, 6, 0, false),
128 51 => (7, ALU_DIV, 10, 7, 0, false),
129 52 => (8, ALU_DIV, 10, 8, 0, false),
130 53 => (9, ALU_DIV, 10, 9, 0, false),
131 54 => (0, ALU_DIV, 10, 0, 0, false),
132 55 => (10, ALU_DIV, 10, 0, 1, false),
133 56 => (5134123, ALU_DIV, 358015, 121913, 14, false),
135 60 => (5, ALU_SUB, -2147483648, 0, 0, true),
136 61 => (-2147483647, ALU_SUB, 1, 0, -2147483648, false),
137 62 => (-2147483647, ALU_ADD, -1, 0, -2147483648, false),
138 63 => (-2147483648, ALU_DIV, 10, 8, -214748364, false),
139 others => (0, ALU_ADD, 0, 0, 0, false)
141 variable checkall : boolean := true;
147 op1 <= (others => '0');
148 op2 <= (others => '0');
153 for i in testmatrix'range loop
155 op1 <= std_logic_vector(to_signed(testmatrix(i).o1,CBITS));
156 opcode <= testmatrix(i).o;
157 op2 <= std_logic_vector(to_signed(testmatrix(i).o2,CBITS));
159 -- berechnung kann los gehen
162 -- warten auf die alu einheit
166 if testmatrix(i).errcase then
167 if (calc_error = '0') then
168 assert(false) report "sollte ein error sein";
169 assert op3 = std_logic_vector(to_signed(testmatrix(i).expected,CBITS))
170 report "" & cinteger'image(testmatrix(i).o1) &
171 " " & integer'image(to_integer(signed(opcode))) &
172 " " & cinteger'image(testmatrix(i).o2) &
173 "/= " & integer'image(to_integer(signed(op3))) &
174 " -- erwartet: " & cinteger'image(testmatrix(i).expected);
177 assert(false) report "testfall war ein error (passt)";
180 if not((op3 = std_logic_vector(to_signed(testmatrix(i).expected,CBITS))) and (opcode /= ALU_DIV or opM = std_logic_vector(to_signed(testmatrix(i).om,CBITS)))) then
181 assert(false) report "" & cinteger'image(testmatrix(i).o1) &
182 " " & integer'image(to_integer(signed(opcode))) &
183 " " & cinteger'image(testmatrix(i).o2) &
184 "/= " & integer'image(to_integer(signed(op3))) &
185 " -- erwartet: " & cinteger'image(testmatrix(i).expected);
196 report "alle testfaelle der ALU waren erfolgreich!";
198 report "einige testfaelle schlugen fehl";
203 end architecture sim;