2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
6 entity pc_communication is
8 sys_clk : in std_logic;
9 sys_res_n : in std_logic;
15 tx_data : out std_logic_vector(7 downto 0);
16 tx_new : out std_logic;
17 tx_done : in std_logic;
20 rx_data : in std_logic_vector(7 downto 0);
21 rx_new : in std_logic;
24 pc_zeile : out hzeile;
25 pc_spalte : out hspalte;
26 pc_get : out std_logic;
27 pc_done : in std_logic;
30 end entity pc_communication;
32 architecture beh of pc_communication is
33 signal spalte, spalte_next : integer range 1 to HSPALTE_MAX + 2;
34 signal zeile , zeile_next : integer range 0 to HZEILE_MAX + 1;
35 signal get, get_next : std_logic;
36 signal new_i, new_i_next : std_logic;
37 signal tx_done_i, tx_done_i_next : std_logic;
38 signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0);
40 type STATE_PC is (IDLE, FETCH, FORWARD, WAIT_UART, UART_DONE, CALC_VAL);
41 signal state, state_next : STATE_PC ;
43 pc_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
44 pc_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
47 tx_done_i_next <= tx_done;
50 sync: process (sys_clk, sys_res_n)
52 if sys_res_n = '0' then
60 elsif rising_edge(sys_clk) then
61 spalte <= spalte_next;
66 tx_done_i <= tx_done_i_next;
67 tx_data_i <= tx_data_i_next;
71 output_pc : process (state, zeile, spalte, tx_data_i, tx_done_i, pc_char)
76 spalte_next <= spalte;
78 tx_data_i_next <= tx_data_i;
86 tx_data_i_next <= pc_char;
88 -- halte pc_get weiterhin high sodass pc_char garantiert gleich bleibt
93 when UART_DONE => null;
97 spalte_next <= spalte + 1;
98 if spalte = HSPALTE_MAX + 1 then
99 tx_data_i_next <= x"0a";
103 zeile_next <= zeile + 1;
104 if zeile = HZEILE_MAX-1 then
109 end process output_pc;
111 next_state_pc : process (btn_a, pc_done, rx_new, rx_data, spalte, state,
112 tx_data_i ,tx_done_i, zeile, pc_char)
117 -- if (rx_new = '1' and rx_data = x"0a") or btn_a = '0' then
118 if (rx_new = '1') or btn_a = '0' then
122 if pc_done = '1' and tx_done_i = '0' then
123 if pc_char = x"00" then
124 state_next <= UART_DONE;
126 state_next <= FORWARD;
130 state_next <= WAIT_UART;
132 if (tx_done_i = '1') then
133 state_next <= UART_DONE;
136 state_next <= CALC_VAL;
138 if spalte = HSPALTE_MAX + 1 and zeile = HZEILE_MAX - 1 then
144 end process next_state_pc;
145 end architecture beh;