2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
6 entity pc_communication is
8 sys_clk : in std_logic;
9 sys_res_n : in std_logic;
13 tx_data : out std_logic_vector(7 downto 0);
14 tx_new : out std_logic;
15 tx_done : in std_logic;
17 rx_data : in std_logic_vector(7 downto 0);
18 rx_new : in std_logic;
20 pc_zeile : out hzeile;
21 pc_spalte : out hspalte;
22 pc_get : out std_logic;
23 pc_done : in std_logic;
26 end entity pc_communication;
28 architecture beh of pc_communication is
29 signal spalte, spalte_next : integer range 1 to HSPALTE_MAX + 2;
30 signal zeile , zeile_next : integer range 0 to HZEILE_MAX + 1;
31 signal get, get_next : std_logic;
32 signal new_i, new_i_next : std_logic;
33 signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0);
35 type STATE_PC is (IDLE, FETCH, FORWARD, UART_DONE, CR, CR_WAIT,
36 NL, NL_WAIT, PRINT_NO1, PRINT_NO1_WAIT, PRINT_NO2, PRINT_NO2_WAIT,
37 PRINT_NO3, PRINT_NO3_WAIT, PRINT_NO4, PRINT_NO4_WAIT, PRINT_NO5,
38 PRINT_NO5_WAIT, PRINT_NO6);
39 signal state, state_next : STATE_PC ;
41 pc_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
42 pc_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
47 sync: process (sys_clk, sys_res_n)
49 if sys_res_n = '0' then
56 elsif rising_edge(sys_clk) then
57 spalte <= spalte_next;
62 tx_data_i <= tx_data_i_next;
66 process (state, zeile, spalte, tx_data_i, tx_done, pc_char, rx_new, btn_a,
68 variable tmp : std_logic_vector(6 downto 0);
72 spalte_next <= spalte;
74 tx_data_i_next <= tx_data_i;
81 if ((rx_new = '1' and rx_data = x"41") or btn_a = '0') and tx_done = '0' then
82 state_next <= PRINT_NO1;
86 tx_data_i_next <= x"28"; -- '('
89 state_next <= PRINT_NO1_WAIT;
91 when PRINT_NO1_WAIT =>
93 state_next <= PRINT_NO2;
96 tx_data_i_next <= zeile2char(std_logic_vector(to_unsigned(zeile,7)), 1);
99 state_next <= PRINT_NO2_WAIT;
101 when PRINT_NO2_WAIT =>
102 if tx_done = '0' then
103 state_next <= PRINT_NO3;
106 tx_data_i_next <= zeile2char(std_logic_vector(to_unsigned(zeile,7)), 2);
108 if tx_done = '1' then
109 state_next <= PRINT_NO3_WAIT;
111 when PRINT_NO3_WAIT =>
112 if tx_done = '0' then
113 state_next <= PRINT_NO4;
116 tx_data_i_next <= x"29"; -- ')'
118 if tx_done = '1' then
119 state_next <= PRINT_NO4_WAIT;
121 when PRINT_NO4_WAIT =>
122 if tx_done = '0' then
123 state_next <= PRINT_NO5;
126 tx_data_i_next <= x"24"; -- '$'
128 if tx_done = '1' then
129 state_next <= PRINT_NO5_WAIT;
131 when PRINT_NO5_WAIT =>
132 if tx_done = '0' then
133 state_next <= PRINT_NO6;
136 tx_data_i_next <= x"20"; -- ' '
138 if tx_done = '1' then
144 if pc_done = '1' and tx_done = '0' then
145 state_next <= FORWARD;
146 if pc_char = x"00" then
147 state_next <= UART_DONE;
151 tx_data_i_next <= pc_char;
153 -- halte pc_get weiterhin high sodass pc_char garantiert
154 -- gleicht bleibt (blockiert history!)
156 if tx_done = '1' then
157 state_next <= UART_DONE;
160 if tx_done = '0' then
162 spalte_next <= spalte + 1;
163 if spalte = HSPALTE_MAX + 1 then
166 zeile_next <= zeile + 1;
170 tx_data_i_next <= x"0a";
172 if tx_done = '1' then
173 state_next <= NL_WAIT;
176 if tx_done = '0' then
180 tx_data_i_next <= x"0d";
182 if tx_done = '1' then
183 state_next <= CR_WAIT;
186 if tx_done = '0' then
187 tmp := std_logic_vector(to_unsigned(zeile,7));
189 -- es handelt sich um eingabe im naechsten schritt
190 -- => print zeilennummer
191 state_next <= PRINT_NO1;
196 if zeile = HZEILE_MAX then
201 end architecture beh;