2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
6 entity pc_communication is
8 sys_clk : in std_logic;
9 sys_res_n : in std_logic;
15 tx_data : out std_logic_vector(7 downto 0);
16 tx_new : out std_logic;
17 tx_done : in std_logic;
20 rx_data : in std_logic_vector(7 downto 0);
21 rx_new : in std_logic;
25 d_spalte : out hspalte;
26 d_get : out std_logic;
27 d_done : in std_logic;
30 end entity pc_communication;
32 architecture beh of pc_communication is
33 signal spalte, spalte_next : integer range 1 to hspalte_max + 1;
34 signal zeile , zeile_next : integer range 1 to hzeile_max + 1;
35 signal get, get_next : std_logic;
36 signal new_i, new_i_next : std_logic;
37 signal tx_done_i, tx_done_i_next : std_logic;
38 signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0);
39 signal s_done, s_done_next : std_logic;
41 type STATE_PC is (IDLE, FETCH, FORWARD, DONE);
42 signal state, state_next : STATE_PC ;
47 d_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
48 d_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
51 tx_done_i_next <= tx_done;
54 sync: process (sys_clk, sys_res_n)
56 if sys_res_n = '0' then
62 tx_data_i <= "00000000";
65 elsif rising_edge(sys_clk) then
66 spalte <= spalte_next;
71 tx_done_i <= tx_done_i_next;
72 tx_data_i <= tx_data_i_next;
73 s_done <= s_done_next;
77 output_pc : process (state, zeile, spalte, tx_data_i, tx_done_i, d_char)
78 variable spalte_up : std_logic;
84 spalte_next <= spalte;
86 tx_data_i_next <= tx_data_i;
94 tx_data_i_next <= d_char;
97 if (tx_done_i = '1') then
105 if spalte_up = '1' then
106 if spalte = hspalte_max then
107 if zeile = hzeile_max then
113 zeile_next <= zeile + 1;
116 spalte_next <= spalte + 1; --overflow here!
121 end process output_pc;
123 next_state_pc : process (state, rx_new, rx_data, btn_a, d_done, tx_done_i, s_done)
128 if (rx_new = '1' and rx_data = x"0a" ) or btn_a = '1' then
132 if (d_done = '1') then
133 state_next <= FORWARD;
134 elsif (s_done = '1') then
138 if (tx_done_i = '1') then
144 end process next_state_pc;
146 end architecture beh;