src/pc_communication.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use work.gen_pkg.all;
   5
   6 entity pc_communication is
   7         port (
   8                 sys_clk : in std_logic;
   9                 sys_res_n : in std_logic;
  10                 --button
  11                 btn_a : in std_logic;
  12                 --uart_tx
  13                 tx_data : out std_logic_vector(7 downto 0);
  14                 tx_new : out std_logic;
  15                 tx_done : in std_logic;
  16                 --uart_rx
  17                 rx_data : in std_logic_vector(7 downto 0);
  18                 rx_new : in std_logic;
  19                 -- History
  20                 pc_zeile : out hzeile;
  21                 pc_spalte : out hspalte;
  22                 pc_get :  out std_logic;
  23                 pc_done : in std_logic;
  24                 pc_char : in hbyte
  25         );
  26 end entity pc_communication;
  27
  28 architecture beh of pc_communication is
  29         signal spalte, spalte_next : integer range 1 to HSPALTE_MAX + 2;
  30         signal zeile , zeile_next : integer range 0 to HZEILE_MAX + 1;
  31         signal get, get_next : std_logic;
  32         signal new_i, new_i_next : std_logic;
  33         signal tx_done_i, tx_done_i_next : std_logic;
  34         signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0);
  35
  36         type STATE_PC is (IDLE, FETCH, FORWARD, UART_DONE, CR, CR_WAIT,
  37                 NL, NL_WAIT, PRINT_NO1, PRINT_NO1_WAIT, PRINT_NO2, PRINT_NO2_WAIT,
  38                 PRINT_NO3, PRINT_NO3_WAIT, PRINT_NO4, PRINT_NO4_WAIT, PRINT_NO5,
  39                 PRINT_NO5_WAIT, PRINT_NO6, PRINT_NO0_WAIT);
  40         signal state, state_next : STATE_PC ;
  41 begin
  42         pc_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
  43         pc_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
  44         pc_get <= get;
  45         tx_new <= new_i;
  46         tx_done_i_next <= tx_done;
  47         tx_data <= tx_data_i;
  48
  49         sync: process (sys_clk, sys_res_n)
  50         begin
  51                 if sys_res_n = '0' then
  52                         state <= IDLE;
  53                         spalte <= 1;
  54                         zeile <= 0;
  55                         get <= '0';
  56                         new_i <= '0';
  57                         tx_data_i <= x"00";
  58                         tx_done_i <= '0';
  59                 elsif rising_edge(sys_clk) then
  60                         spalte <= spalte_next;
  61                         zeile <= zeile_next;
  62                         state <= state_next;
  63                         get <= get_next;
  64                         new_i <= new_i_next;
  65                         tx_done_i <= tx_done_i_next;
  66                         tx_data_i <= tx_data_i_next;
  67                 end if;
  68         end process sync;
  69
  70         process (state, zeile, spalte, tx_data_i, tx_done_i, pc_char, rx_new, btn_a,
  71                         pc_done, rx_data)
  72                 variable tmp : std_logic_vector(6 downto 0);
  73         begin
  74                 get_next <= '0';
  75                 new_i_next <= '0';
  76                 spalte_next <= spalte;
  77                 zeile_next <= zeile;
  78                 tx_data_i_next <= tx_data_i;
  79
  80                 state_next <= state;
  81                 case state is
  82                         when IDLE =>
  83                                 if (rx_new = '1' and rx_data = x"0a") or btn_a = '0' then
  84                                         state_next <= PRINT_NO0_WAIT;
  85                                 end if;
  86
  87                         when PRINT_NO0_WAIT =>
  88                                 if tx_done_i = '0' then
  89                                         state_next <= PRINT_NO1;
  90                                 end if;
  91                         when PRINT_NO1 =>
  92                                 tx_data_i_next <= x"28"; -- '('
  93                                 new_i_next <= '1';
  94                                 if tx_done_i = '1' then
  95                                         state_next <= PRINT_NO1_WAIT;
  96                                 end if;
  97                         when PRINT_NO1_WAIT =>
  98                                 if tx_done_i = '0' then
  99                                         state_next <= PRINT_NO2;
 100                                 end if;
 101                         when PRINT_NO2 =>
 102                                 tx_data_i_next <= zeile2char(std_logic_vector(to_unsigned(zeile,7)), 1);
 103                                 new_i_next <= '1';
 104                                 if tx_done_i = '1' then
 105                                         state_next <= PRINT_NO2_WAIT;
 106                                 end if;
 107                         when PRINT_NO2_WAIT =>
 108                                 if tx_done_i = '0' then
 109                                         state_next <= PRINT_NO3;
 110                                 end if;
 111                         when PRINT_NO3 =>
 112                                 tx_data_i_next <= zeile2char(std_logic_vector(to_unsigned(zeile,7)), 2);
 113                                 new_i_next <= '1';
 114                                 if tx_done_i = '1' then
 115                                         state_next <= PRINT_NO3_WAIT;
 116                                 end if;
 117                         when PRINT_NO3_WAIT =>
 118                                 if tx_done_i = '0' then
 119                                         state_next <= PRINT_NO4;
 120                                 end if;
 121                         when PRINT_NO4 =>
 122                                 tx_data_i_next <= x"29"; -- ')'
 123                                 new_i_next <= '1';
 124                                 if tx_done_i = '1' then
 125                                         state_next <= PRINT_NO4_WAIT;
 126                                 end if;
 127                         when PRINT_NO4_WAIT =>
 128                                 if tx_done_i = '0' then
 129                                         state_next <= PRINT_NO5;
 130                                 end if;
 131                         when PRINT_NO5 =>
 132                                 tx_data_i_next <= x"24"; -- '$'
 133                                 new_i_next <= '1';
 134                                 if tx_done_i = '1' then
 135                                         state_next <= PRINT_NO5_WAIT;
 136                                 end if;
 137                         when PRINT_NO5_WAIT =>
 138                                 if tx_done_i = '0' then
 139                                         state_next <= PRINT_NO6;
 140                                 end if;
 141                         when PRINT_NO6 =>
 142                                 tx_data_i_next <= x"20"; -- ' '
 143                                 new_i_next <= '1';
 144                                 if tx_done_i = '1' then
 145                                         state_next <= FETCH;
 146                                 end if;
 147
 148                         when FETCH =>
 149                                 get_next <= '1';
 150                                 if pc_done = '1' and tx_done_i = '0' then
 151                                         state_next <= FORWARD;
 152                                         if pc_char = x"00" then
 153                                                 state_next <= UART_DONE;
 154                                         end if;
 155                                 end if;
 156                         when FORWARD =>
 157                                 tx_data_i_next <= pc_char;
 158                                 new_i_next <= '1';
 159                                 -- halte pc_get weiterhin high sodass pc_char garantiert
 160                                 -- gleicht bleibt (blockiert history!)
 161                                 get_next <= '1';
 162                                 if tx_done_i = '1' then
 163                                         state_next <= UART_DONE;
 164                                 end if;
 165                         when UART_DONE =>
 166                                 if tx_done_i = '0' then
 167                                         state_next <= FETCH;
 168                                         spalte_next <= spalte + 1;
 169                                         if spalte = HSPALTE_MAX + 1 then
 170                                                 state_next <= NL;
 171                                                 spalte_next <= 1;
 172                                                 zeile_next <= zeile + 1;
 173                                         end if;
 174                                 end if;
 175                         when NL =>
 176                                 tx_data_i_next <= x"0a";
 177                                 new_i_next <= '1';
 178                                 if tx_done_i = '1' then
 179                                         state_next <= NL_WAIT;
 180                                 end if;
 181                         when NL_WAIT =>
 182                                 state_next <= CR;
 183                         when CR =>
 184                                 tx_data_i_next <= x"0d";
 185                                 new_i_next <= '1';
 186                                 if tx_done_i = '1' then
 187                                         state_next <= CR_WAIT;
 188                                 end if;
 189                         when CR_WAIT =>
 190                                 tmp := std_logic_vector(to_unsigned(zeile,7));
 191                                 if tmp(0) = '0' then
 192                                         -- es handelt sich um eingabe im naechsten schritt
 193                                         -- => print zeilennummer
 194                                         state_next <= PRINT_NO0_WAIT;
 195                                 else
 196                                         state_next <= FETCH;
 197                                 end if;
 198                                 if zeile = HZEILE_MAX then
 199                                         state_next <= IDLE;
 200                                         zeile_next <= 0;
 201                                         spalte_next <= 1;
 202                                 end if;
 203                 end case;
 204         end process;
 205 end architecture beh;