src/pc_communication.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use work.gen_pkg.all;
   5
   6 entity pc_communication is
   7         port (
   8                 sys_clk : in std_logic;
   9                 sys_res_n : in std_logic;
  10                 --button
  11                 btn_a : in std_logic;
  12                 --uart_tx
  13                 tx_data : out std_logic_vector(7 downto 0);
  14                 tx_new : out std_logic;
  15                 tx_done : in std_logic;
  16                 --uart_rx
  17                 rx_data : in std_logic_vector(7 downto 0);
  18                 rx_new : in std_logic;
  19                 -- History
  20                 pc_zeile : out hzeile;
  21                 pc_spalte : out hspalte;
  22                 pc_get :  out std_logic;
  23                 pc_done : in std_logic;
  24                 pc_char : in hbyte
  25         );
  26 end entity pc_communication;
  27
  28 architecture beh of pc_communication is
  29         signal spalte, spalte_next : integer range 1 to HSPALTE_MAX + 2;
  30         signal zeile , zeile_next : integer range 0 to HZEILE_MAX + 1;
  31         signal get, get_next : std_logic;
  32         signal new_i, new_i_next : std_logic;
  33         signal tx_done_i, tx_done_i_next : std_logic;
  34         signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0);
  35
  36         type STATE_PC is (IDLE, FETCH, FORWARD, UART_DONE, CR, CR_WAIT,
  37                 NL, NL_WAIT, PRINT_NO1, PRINT_NO1_WAIT, PRINT_NO2, PRINT_NO2_WAIT,
  38                 PRINT_NO3, PRINT_NO3_WAIT, PRINT_NO4, PRINT_NO4_WAIT, PRINT_NO5,
  39                 PRINT_NO5_WAIT, PRINT_NO6);
  40         signal state, state_next : STATE_PC ;
  41 begin
  42         pc_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
  43         pc_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
  44         pc_get <= get;
  45         tx_new <= new_i;
  46         tx_done_i_next <= tx_done;
  47         tx_data <= tx_data_i;
  48
  49         sync: process (sys_clk, sys_res_n)
  50         begin
  51                 if sys_res_n = '0' then
  52                         state <= IDLE;
  53                         spalte <= 1;
  54                         zeile <= 0;
  55                         get <= '0';
  56                         new_i <= '0';
  57                         tx_data_i <= x"00";
  58                         tx_done_i <= '0';
  59                 elsif rising_edge(sys_clk) then
  60                         spalte <= spalte_next;
  61                         zeile <= zeile_next;
  62                         state <= state_next;
  63                         get <= get_next;
  64                         new_i <= new_i_next;
  65                         tx_done_i <= tx_done_i_next;
  66                         tx_data_i <= tx_data_i_next;
  67                 end if;
  68         end process sync;
  69
  70         process (state, zeile, spalte, tx_data_i, tx_done_i, pc_char, rx_new, btn_a,
  71                         pc_done, rx_data)
  72                 variable tmp : std_logic_vector(6 downto 0);
  73         begin
  74                 get_next <= '0';
  75                 new_i_next <= '0';
  76                 spalte_next <= spalte;
  77                 zeile_next <= zeile;
  78                 tx_data_i_next <= tx_data_i;
  79
  80                 state_next <= state;
  81                 case state is
  82                         when IDLE =>
  83                                 zeile_next <= 0;
  84                                 spalte_next <= 1;
  85                                 if ((rx_new = '1' and rx_data = x"41") or btn_a = '0') and tx_done_i = '0' then
  86                                         state_next <= PRINT_NO1;
  87                                 end if;
  88
  89                         when PRINT_NO1 =>
  90                                 tx_data_i_next <= x"28"; -- '('
  91                                 new_i_next <= '1';
  92                                 if tx_done_i = '1' then
  93                                         state_next <= PRINT_NO1_WAIT;
  94                                 end if;
  95                         when PRINT_NO1_WAIT =>
  96                                 if tx_done_i = '0' then
  97                                         state_next <= PRINT_NO2;
  98                                 end if;
  99                         when PRINT_NO2 =>
 100                                 tx_data_i_next <= zeile2char(std_logic_vector(to_unsigned(zeile,7)), 1);
 101                                 new_i_next <= '1';
 102                                 if tx_done_i = '1' then
 103                                         state_next <= PRINT_NO2_WAIT;
 104                                 end if;
 105                         when PRINT_NO2_WAIT =>
 106                                 if tx_done_i = '0' then
 107                                         state_next <= PRINT_NO3;
 108                                 end if;
 109                         when PRINT_NO3 =>
 110                                 tx_data_i_next <= zeile2char(std_logic_vector(to_unsigned(zeile,7)), 2);
 111                                 new_i_next <= '1';
 112                                 if tx_done_i = '1' then
 113                                         state_next <= PRINT_NO3_WAIT;
 114                                 end if;
 115                         when PRINT_NO3_WAIT =>
 116                                 if tx_done_i = '0' then
 117                                         state_next <= PRINT_NO4;
 118                                 end if;
 119                         when PRINT_NO4 =>
 120                                 tx_data_i_next <= x"29"; -- ')'
 121                                 new_i_next <= '1';
 122                                 if tx_done_i = '1' then
 123                                         state_next <= PRINT_NO4_WAIT;
 124                                 end if;
 125                         when PRINT_NO4_WAIT =>
 126                                 if tx_done_i = '0' then
 127                                         state_next <= PRINT_NO5;
 128                                 end if;
 129                         when PRINT_NO5 =>
 130                                 tx_data_i_next <= x"24"; -- '$'
 131                                 new_i_next <= '1';
 132                                 if tx_done_i = '1' then
 133                                         state_next <= PRINT_NO5_WAIT;
 134                                 end if;
 135                         when PRINT_NO5_WAIT =>
 136                                 if tx_done_i = '0' then
 137                                         state_next <= PRINT_NO6;
 138                                 end if;
 139                         when PRINT_NO6 =>
 140                                 tx_data_i_next <= x"20"; -- ' '
 141                                 new_i_next <= '1';
 142                                 if tx_done_i = '1' then
 143                                         state_next <= FETCH;
 144                                 end if;
 145
 146                         when FETCH =>
 147                                 get_next <= '1';
 148                                 if pc_done = '1' and tx_done_i = '0' then
 149                                         state_next <= FORWARD;
 150                                         if pc_char = x"00" then
 151                                                 state_next <= UART_DONE;
 152                                         end if;
 153                                 end if;
 154                         when FORWARD =>
 155                                 tx_data_i_next <= pc_char;
 156                                 new_i_next <= '1';
 157                                 -- halte pc_get weiterhin high sodass pc_char garantiert
 158                                 -- gleicht bleibt (blockiert history!)
 159                                 get_next <= '1';
 160                                 if tx_done_i = '1' then
 161                                         state_next <= UART_DONE;
 162                                 end if;
 163                         when UART_DONE =>
 164                                 if tx_done_i = '0' then
 165                                         state_next <= FETCH;
 166                                         spalte_next <= spalte + 1;
 167                                         if spalte = HSPALTE_MAX + 1 then
 168                                                 state_next <= NL;
 169                                                 spalte_next <= 1;
 170                                                 zeile_next <= zeile + 1;
 171                                         end if;
 172                                 end if;
 173                         when NL =>
 174                                 tx_data_i_next <= x"0a";
 175                                 new_i_next <= '1';
 176                                 if tx_done_i = '1' then
 177                                         state_next <= NL_WAIT;
 178                                 end if;
 179                         when NL_WAIT =>
 180                                 if tx_done_i = '0' then
 181                                         state_next <= CR;
 182                                 end if;
 183                         when CR =>
 184                                 tx_data_i_next <= x"0d";
 185                                 new_i_next <= '1';
 186                                 if tx_done_i = '1' then
 187                                         state_next <= CR_WAIT;
 188                                 end if;
 189                         when CR_WAIT =>
 190                                 if tx_done_i = '0' then
 191                                         tmp := std_logic_vector(to_unsigned(zeile,7));
 192                                         if tmp(0) = '0' then
 193                                                 -- es handelt sich um eingabe im naechsten schritt
 194                                                 -- => print zeilennummer
 195                                                 state_next <= PRINT_NO1;
 196                                         else
 197                                                 state_next <= FETCH;
 198                                         end if;
 199                                 end if;
 200                                 if zeile = HZEILE_MAX then
 201                                         state_next <= IDLE;
 202                                 end if;
 203                 end case;
 204         end process;
 205 end architecture beh;