2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
6 entity pc_communication is
8 sys_clk : in std_logic;
9 sys_res_n : in std_logic;
15 tx_data : out std_logic_vector(7 downto 0);
16 tx_new : out std_logic;
17 tx_done : in std_logic;
20 rx_data : in std_logic_vector(7 downto 0);
21 rx_new : in std_logic;
25 d_spalte : out hspalte;
26 d_get : out std_logic;
27 d_done : in std_logic;
30 end entity pc_communication;
32 architecture beh of pc_communication is
33 signal spalte, spalte_next : integer range 1 to hspalte_max + 1;
34 signal zeile , zeile_next : integer range 1 to hzeile_max + 1;
35 signal spalte_up, spalte_up_next : std_logic;
36 signal get, get_next : std_logic;
37 signal new_i, new_i_next : std_logic;
38 signal tx_done_i, tx_done_i_next : std_logic;
39 signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0);
40 signal s_done, s_done_next : std_logic;
42 signal char, char_next : hbyte;
43 signal char_en : std_logic;
44 type STATE_PC is (IDLE, FETCH, FORWARD, DONE);
45 signal state, state_next : STATE_PC ;
50 d_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
51 d_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
55 tx_done_i_next <= tx_done;
58 sync: process (sys_clk, sys_res_n)
60 if sys_res_n = '0' then
66 tx_data_i <= "00000000";
70 elsif rising_edge(sys_clk) then
71 spalte <= spalte_next;
76 tx_done_i <= tx_done_i_next;
77 tx_data_i <= tx_data_i_next;
78 spalte_up <= spalte_up_next;
79 s_done <= s_done_next;
80 if (char_en = '1') then
86 output_pc : process (state, zeile, spalte, char, tx_data_i, tx_done_i, spalte_up)
91 spalte_up_next <= '0';
93 spalte_next <= spalte;
95 tx_data_i_next <= tx_data_i;
98 if spalte_up = '1' then
99 if spalte = hspalte_max then
100 if zeile = hzeile_max then
106 zeile_next <= zeile + 1;
109 spalte_next <= spalte + 1; --overflow here!
121 tx_data_i_next <= char;
123 if (tx_done_i = '1') then
124 spalte_up_next <= '1';
130 end process output_pc;
132 next_state_pc : process (state, rx_new, rx_data, btn_a, d_done, tx_done_i, s_done)
137 if (rx_new = '1' and rx_data = x"0a" ) or btn_a = '1' then
141 if (d_done = '1') then
142 state_next <= FORWARD;
143 elsif (s_done = '1') then
147 if (tx_done_i = '1') then
153 end process next_state_pc;
155 end architecture beh;