pc and uart compile
[hwmod.git] / src / pc_communication.vhd
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4 use work.gen_pkg.all;
5
6 entity pc_communication is
7         port (
8                 sys_clk : in std_logic;
9                 sys_res_n : in std_logic;
10
11                 --button
12                 btn_a : in std_logic;
13
14                 --uart_tx
15                 tx_data : out std_logic_vector(7 downto 0);
16                 tx_new : out std_logic;
17                 tx_done : in std_logic;
18
19                 --uart_rx
20                 rx_data : in std_logic_vector(7 downto 0); --not really required
21                 rx_new : in std_logic;
22
23                 -- History
24                 d_zeile : out hzeile;
25                 d_spalte : out hspalte;
26                 d_get :  out std_logic;
27                 d_done : in std_logic;
28                 d_char : in hbyte
29         );
30 end entity pc_communication;
31
32 architecture beh of pc_communication is
33         signal push_history, push_history_next : std_logic;
34
35         signal spalte, spalte_next : hspalte;
36         signal zeile , zeile_next : hzeile;
37         signal spalte_up, spalte_up_next : std_logic;
38
39         signal char, char_next : hbyte;
40         signal char_en : std_logic;
41         type STATE_PC is (IDLE, FETCH, FORWARD, DONE);
42         signal state, state_next : STATE_PC ;
43
44 begin
45
46         sync: process (sys_clk, sys_res_n)
47         begin
48                 if sys_res_n = '0' then
49                         state <= IDLE;
50                         push_history <= '0';
51                         spalte <= "0000000";
52                         zeile <= "0000000";
53                 elsif rising_edge(sys_clk) then
54                         push_history <= push_history_next;
55                         spalte <= spalte_next;
56                         zeile <= zeile_next;
57                         state <= state_next;
58                         if (char_en = '1') then
59                                 state <= state_next;
60                         end if;
61                 end if;
62         end process sync;
63
64         process (spalte_up)
65         variable spalte_tmp, zeile_tmp : integer;
66         begin
67                 if (spalte_up = '1') then
68                         if (spalte > X"45") then
69                                 spalte_next <= "0000000";
70                                 zeile_tmp := to_integer(unsigned(zeile));
71                                 zeile_tmp := zeile_tmp + 1;
72                                 zeile_next <= hbyte(to_unsigned(zeile_tmp,8));
73                         else
74                                 spalte_tmp := to_integer(unsigned(spalte));
75                                 spalte_tmp := spalte_tmp + 1;
76                                 spalte_next <= hbyte(to_unsigned(spalte_tmp,8));
77                                 zeile_next <= zeile;
78                         end if;
79                         spalte_up <= '0';
80                 end if;
81         end process;
82
83         async_push_history : process (rx_new, rx_data, btn_a)
84         begin
85                 if rx_new = '1' then
86                         if rx_data = X"41" then
87                                 push_history_next <= '1';
88                         else
89                                 push_history_next <= '0';
90                         end if;
91                 elsif btn_a = '1' then
92                                 push_history_next <= '1';
93                 else
94                         push_history_next <= '0';
95                 end if;
96         end process async_push_history;
97
98         output_pc : process (zeile, spalte)
99         begin
100                 case state is 
101                         when IDLE =>
102                                 spalte_next <= "0000000";
103                                 zeile_next <= "0000000";
104                         when FETCH =>
105                                 d_zeile <= zeile;
106                                 d_spalte <= spalte;
107                                 d_get <= '1';
108                                 char_en <= '1';
109                                 -- wait for timer overflow
110                                 -- increment counter
111                         when FORWARD =>
112                                 char_en <= '0';
113                                 tx_data <= char;
114                                 tx_new <= '1';
115                         when DONE =>
116                                 null;
117                                 -- be there for a single cycle and then 
118                 end case;
119         end process output_pc;
120
121         next_state_pc : process (rx_new, btn_a)
122         begin
123                 case state is
124                         when IDLE =>
125                                 if rx_new= '1' or btn_a = '1' then
126                                         state_next <= FETCH;
127                                         char <= d_char; --latch
128                                 end if;
129                         when FETCH =>
130                                 if (d_done = '1') then
131                                         state_next <= FORWARD;
132                                 end if;
133                         when FORWARD =>
134                                 if (tx_done = '1') then
135                                         state_next <= FETCH;
136                                 end if;
137                         when DONE =>
138                                 -- be there for a single cycle and then 
139                                 state_next <= IDLE;
140                 end case;
141         end process next_state_pc;
142
143 end architecture beh;