src/pc_communication.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use work.gen_pkg.all;
   5
   6 entity pc_communication is
   7         port (
   8                 sys_clk : in std_logic;
   9                 sys_res_n : in std_logic;
  10
  11                 --button
  12                 btn_a : in std_logic;
  13
  14                 --uart_tx
  15                 tx_data : out std_logic_vector(7 downto 0);
  16                 tx_new : out std_logic;
  17                 tx_done : in std_logic;
  18
  19                 --uart_rx
  20                 rx_data : in std_logic_vector(7 downto 0); --not really required
  21                 rx_new : in std_logic;
  22
  23                 -- History
  24                 d_zeile : out hzeile;
  25                 d_spalte : out hspalte;
  26                 d_get :  out std_logic;
  27                 d_done : in std_logic;
  28                 d_char : in hbyte
  29         );
  30 end entity pc_communication;
  31
  32 architecture beh of pc_communication is
  33         signal push_history, push_history_next : std_logic;
  34
  35         signal spalte, spalte_next : hspalte;
  36         signal zeile , zeile_next : hzeile;
  37         signal spalte_up, spalte_up_next : std_logic;
  38
  39         signal char, char_next : hbyte;
  40         signal char_en : std_logic;
  41         type STATE_PC is (IDLE, FETCH, FORWARD, DONE);
  42         signal state, state_next : STATE_PC ;
  43
  44 begin
  45
  46         sync: process (sys_clk, sys_res_n)
  47         begin
  48                 if sys_res_n = '0' then
  49                         state <= IDLE;
  50                         push_history <= '0';
  51                         spalte <= "0000000";
  52                         spalte_next <= "0000000";
  53                         zeile <= "0000000";
  54                         zeile_next <= "0000000";
  55                         d_get <= '0';
  56                         tx_new <= '0';
  57                         tx_data <= "00000000";
  58                 elsif rising_edge(sys_clk) then
  59                         push_history <= push_history_next;
  60                         spalte <= spalte_next;
  61                         zeile <= zeile_next;
  62                         state <= state_next;
  63                         if (char_en = '1') then
  64                                 state <= state_next;
  65                         end if;
  66                 end if;
  67         end process sync;
  68
  69         process (spalte_up)
  70         variable spalte_tmp, zeile_tmp : integer;
  71         variable spalte2_tmp, zeile2_tmp : std_logic_vector(7 downto 0);
  72         begin
  73                 if (spalte_up = '1') then
  74                         if (spalte > X"45") then
  75                                 spalte_next <= "0000000";
  76                                 zeile_tmp := to_integer(unsigned(zeile)) + 1;
  77                                 zeile2_tmp := std_logic_vector(to_unsigned(zeile_tmp,8));
  78                                 zeile_next <= hzeile(zeile2_tmp(6 downto 0));
  79                         else
  80                                 spalte_tmp := to_integer(unsigned(spalte)) + 1;
  81                                 spalte2_tmp := std_logic_vector(to_unsigned(spalte_tmp,8));
  82                                 spalte_next <= hspalte(spalte2_tmp(6 downto 0));
  83
  84                                 zeile_next <= zeile;
  85                         end if;
  86                         spalte_up <= '0';
  87                 end if;
  88         end process;
  89
  90         async_push_history : process (rx_new, rx_data, btn_a)
  91         begin
  92                 if rx_new = '1' then
  93                         if rx_data = X"41" then
  94                                 push_history_next <= '1';
  95                         else
  96                                 push_history_next <= '0';
  97                         end if;
  98                 elsif btn_a = '1' then
  99                                 push_history_next <= '1';
 100                 else
 101                         push_history_next <= '0';
 102                 end if;
 103         end process async_push_history;
 104
 105         output_pc : process (state, zeile, spalte, char)
 106         begin
 107                 d_get <= '0';
 108                 spalte_next <= "0000000";
 109                 zeile_next <= "0000000";
 110                 case state is
 111                         when IDLE =>
 112                                 null;
 113                         when FETCH =>
 114                                 d_zeile <= zeile_next;
 115                                 d_spalte <= spalte_next;
 116                                 d_get <= '1';
 117                                 char_en <= '1';
 118                                 -- wait for timer overflow
 119                                 -- increment counter
 120                         when FORWARD =>
 121                                 char_en <= '0';
 122                                 tx_data <= char;
 123                                 tx_new <= '1';
 124                         when DONE =>
 125                                 null;
 126                                 -- be there for a single cycle and then
 127                 end case;
 128         end process output_pc;
 129
 130         next_state_pc : process (rx_new, btn_a, d_done, tx_done)
 131         begin
 132                 spalte_up <= '0';
 133                 case state is
 134                         when IDLE =>
 135                                 if rx_new = '1' or btn_a = '1' then
 136                                         state_next <= FETCH;
 137                                         char <= d_char; --latch
 138                                 end if;
 139                         when FETCH =>
 140                                 if (d_done = '1') then
 141                                         state_next <= FORWARD;
 142                                 end if;
 143                         when FORWARD =>
 144                                 if (tx_done = '1') then
 145                                         state_next <= FETCH;
 146                                         spalte_up <= '1';
 147                                 end if;
 148                         when DONE =>
 149                                 -- be there for a single cycle and then
 150                                 state_next <= IDLE;
 151                 end case;
 152         end process next_state_pc;
 153
 154 end architecture beh;