src/pc_communication.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use work.gen_pkg.all;
   5
   6 entity pc_communication is
   7         port (
   8                 sys_clk : in std_logic;
   9                 sys_res_n : in std_logic;
  10
  11                 --button
  12                 btn_a : in std_logic;
  13
  14                 --uart_tx
  15                 tx_data : out std_logic_vector(7 downto 0);
  16                 tx_new : out std_logic;
  17                 tx_done : in std_logic;
  18
  19                 --uart_rx
  20                 rx_data : in std_logic_vector(7 downto 0); --not really required
  21                 rx_new : in std_logic;
  22
  23                 -- History
  24                 d_zeile : out hzeile;
  25                 d_spalte : out hspalte;
  26                 d_get :  out std_logic;
  27                 d_done : in std_logic;
  28                 d_char : in hbyte
  29         );
  30 end entity pc_communication;
  31
  32 architecture beh of pc_communication is
  33         signal push_history, push_history_next : std_logic;
  34
  35         signal spalte, spalte_next : integer range 0 to 71;
  36         signal zeile , zeile_next : integer range 0 to 71;
  37         signal spalte_up, spalte_up_next : std_logic;
  38         signal get, get_next : std_logic;
  39         signal new_i, new_i_next : std_logic;
  40         signal tx_done_i, tx_done_i_next : std_logic;
  41         signal d_done_i, d_done_i_next : std_logic;
  42
  43         signal char, char_next : hbyte;
  44         signal char_en : std_logic;
  45         type STATE_PC is (IDLE, FETCH, FORWARD, DONE);
  46         signal state, state_next : STATE_PC ;
  47
  48 begin
  49
  50
  51         d_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
  52         d_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
  53         d_get <= get;
  54         char_next <= d_char;
  55         tx_new <= new_i;
  56         d_done_i <= d_done;
  57         tx_done_i <= tx_done;
  58
  59         sync: process (sys_clk, sys_res_n)
  60         begin
  61                 if sys_res_n = '0' then
  62                         state <= IDLE;
  63                         push_history <= '0';
  64                         spalte <= 0;
  65                         zeile <= 0;
  66                         get <= '0';
  67                         new_i <= '0';
  68                         tx_data <= "00000000";
  69                         spalte_up <= '0';
  70                 elsif rising_edge(sys_clk) then
  71                         push_history <= push_history_next;
  72                         spalte <= spalte_next;
  73                         zeile <= zeile_next;
  74                         state <= state_next;
  75                         get <= get_next;
  76                         new_i <= new_i_next;
  77                         spalte_up <= spalte_up_next;
  78                         if (char_en = '1') then
  79                                 char <= char_next;
  80                         end if;
  81                 end if;
  82         end process sync;
  83
  84         process (spalte_up, spalte, zeile)
  85         begin
  86                 if (spalte_up = '1') then
  87                         if (spalte > 71) then
  88                                 spalte_next <= 0;
  89                                 zeile_next <= zeile + 1;
  90                         else
  91                                 spalte_next <= spalte + 1;
  92                                 zeile_next <= zeile;
  93                         end if;
  94                 else
  95                         spalte_next <= spalte;
  96                         zeile_next <= zeile;
  97                 end if;
  98         end process;
  99
 100         async_push_history : process (rx_new, rx_data, btn_a)
 101         begin
 102                 if rx_new = '1' then
 103                         if rx_data = X"41" then
 104                                 push_history_next <= '1';
 105                         else
 106                                 push_history_next <= '0';
 107                         end if;
 108                 elsif btn_a = '1' then
 109                                 push_history_next <= '1';
 110                 else
 111                         push_history_next <= '0';
 112                 end if;
 113         end process async_push_history;
 114
 115         output_pc : process (state, zeile, spalte, char)
 116         begin
 117                 get_next <= '0';
 118                 new_i_next <= '0';
 119                 spalte_up_next <= '0';
 120                 case state is
 121                         when IDLE =>
 122                                 null;
 123                         when FETCH =>
 124                                 get_next <= '1';
 125                                 char_en <= '1';
 126                         when FORWARD =>
 127                                 char_en <= '0';
 128                                 tx_data <= char;
 129                                 new_i_next <= '1';
 130                                 if (tx_done = '1') then
 131                                         spalte_up_next <= '1';
 132                                 end if;
 133                         when DONE =>
 134                                 null;
 135                 end case;
 136         end process output_pc;
 137
 138         next_state_pc : process (rx_new, btn_a, d_done, tx_done)
 139         begin
 140                 case state is
 141                         when IDLE =>
 142                                 if rx_new = '1' or btn_a = '1' then
 143                                         state_next <= FETCH;
 144
 145                                 end if;
 146                         when FETCH =>
 147                                 if (d_done = '1') then
 148                                         state_next <= FORWARD;
 149                                 end if;
 150                         when FORWARD =>
 151                                 if (tx_done = '1') then
 152                                         state_next <= FETCH;
 153                                 end if;
 154                         when DONE =>
 155                                 state_next <= IDLE;
 156                 end case;
 157         end process next_state_pc;
 158
 159 end architecture beh;