src/pc_communication.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use work.gen_pkg.all;
   5
   6 entity pc_communication is
   7         port (
   8                 sys_clk : in std_logic;
   9                 sys_res_n : in std_logic;
  10
  11                 --button
  12                 btn_a : in std_logic;
  13
  14                 --uart_tx
  15                 tx_data : out std_logic_vector(7 downto 0);
  16                 tx_new : out std_logic;
  17                 tx_done : in std_logic;
  18
  19                 --uart_rx
  20                 rx_data : in std_logic_vector(7 downto 0); --not really required
  21                 rx_new : in std_logic;
  22
  23                 -- History
  24                 d_zeile : out hzeile;
  25                 d_spalte : out hspalte;
  26                 d_get :  out std_logic;
  27                 d_done : in std_logic;
  28                 d_char : in hbyte
  29         );
  30 end entity pc_communication;
  31
  32 architecture beh of pc_communication is
  33         signal push_history, push_history_next : std_logic;
  34
  35         signal spalte, spalte_next : integer range 1 to 73;
  36         signal zeile , zeile_next : integer range 1 to 73;
  37         signal spalte_up, spalte_up_next : std_logic;
  38         signal get, get_next : std_logic;
  39         signal new_i, new_i_next : std_logic;
  40         signal tx_done_i, tx_done_i_next : std_logic;
  41         signal d_done_i : std_logic;
  42
  43         signal char, char_next : hbyte;
  44         signal char_en : std_logic;
  45         type STATE_PC is (IDLE, FETCH, FORWARD, DONE);
  46         signal state, state_next : STATE_PC ;
  47
  48 begin
  49
  50
  51         d_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
  52         d_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
  53         d_get <= get;
  54         char_next <= d_char;
  55         tx_new <= new_i;
  56         d_done_i <= d_done;
  57         tx_done_i_next <= tx_done;
  58
  59         sync: process (sys_clk, sys_res_n)
  60         begin
  61                 if sys_res_n = '0' then
  62                         state <= IDLE;
  63                         push_history <= '0';
  64                         spalte <= 1;
  65                         zeile <= 1;
  66                         get <= '0';
  67                         new_i <= '0';
  68                         tx_data <= "00000000";
  69                         spalte_up <= '0';
  70                         tx_done_i <= '0';
  71                 elsif rising_edge(sys_clk) then
  72                         push_history <= push_history_next;
  73                         spalte <= spalte_next;
  74                         zeile <= zeile_next;
  75                         state <= state_next;
  76                         get <= get_next;
  77                         new_i <= new_i_next;
  78                         tx_done_i <= tx_done_i_next;
  79                         spalte_up <= spalte_up_next;
  80                         if (char_en = '1') then
  81                                 char <= char_next;
  82                         end if;
  83                 end if;
  84         end process sync;
  85
  86         process (spalte_up, spalte, zeile)
  87         begin
  88                 if (spalte_up = '1') then
  89                         if (spalte > 72) then
  90                                 if zeile + 1 > 50 then
  91                                         spalte_next <= 1;
  92                                         zeile_next <= 1;
  93                                         --done <= '1'; lets assume this false
  94                                         assert false severity failure;
  95                                 else
  96                                         spalte_next <= 1;
  97                                         zeile_next <= zeile + 1;
  98                                 end if;
  99                         else
 100                                 spalte_next <= spalte + 1; --overflow here!
 101                                 zeile_next <= zeile;
 102                         end if;
 103                 else
 104                         spalte_next <= spalte;
 105                         zeile_next <= zeile;
 106                 end if;
 107         end process;
 108
 109         async_push_history : process (rx_new, rx_data, btn_a)
 110         begin
 111                 if rx_new = '1' then
 112                         if rx_data = X"41" then
 113                                 push_history_next <= '1';
 114                         else
 115                                 push_history_next <= '0';
 116                         end if;
 117                 elsif btn_a = '1' then
 118                                 push_history_next <= '1';
 119                 else
 120                         push_history_next <= '0';
 121                 end if;
 122         end process async_push_history;
 123
 124         output_pc : process (state, zeile, spalte, char, tx_done_i)
 125         begin
 126                 get_next <= '0';
 127                 new_i_next <= '0';
 128                 spalte_up_next <= '0';
 129                 case state is
 130                         when IDLE =>
 131                                 null;
 132                         when FETCH =>
 133                                 get_next <= '1';
 134                                 char_en <= '1';
 135                         when FORWARD =>
 136                                 char_en <= '0';
 137                                 tx_data <= char;
 138                                 new_i_next <= '1';
 139                                 if (tx_done_i = '1') then
 140                                         spalte_up_next <= '1';
 141                                 end if;
 142                         when DONE =>
 143                                 null;
 144                 end case;
 145         end process output_pc;
 146
 147         next_state_pc : process (rx_new, btn_a, d_done, tx_done_i)
 148         begin
 149                 case state is
 150                         when IDLE =>
 151                                 if rx_new = '1' or btn_a = '1' then
 152                                         state_next <= FETCH;
 153
 154                                 end if;
 155                         when FETCH =>
 156                                 if (d_done = '1') then
 157                                         state_next <= FORWARD;
 158                                 end if;
 159                         when FORWARD =>
 160                                 if (tx_done_i = '1') then
 161                                         state_next <= FETCH;
 162                                 end if;
 163                         when DONE =>
 164                                 state_next <= IDLE;
 165                 end case;
 166         end process next_state_pc;
 167
 168 end architecture beh;