src/pc_communication.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use work.gen_pkg.all;
   5
   6 entity pc_communication is
   7         port (
   8                 sys_clk : in std_logic;
   9                 sys_res_n : in std_logic;
  10
  11                 --button
  12                 btn_a : in std_logic;
  13
  14                 --uart_tx
  15                 tx_data : out std_logic_vector(7 downto 0);
  16                 tx_new : out std_logic;
  17                 tx_done : in std_logic;
  18
  19                 --uart_rx
  20                 rx_data : in std_logic_vector(7 downto 0);
  21                 rx_new : in std_logic;
  22
  23                 -- History
  24                 d_zeile : out hzeile;
  25                 d_spalte : out hspalte;
  26                 d_get :  out std_logic;
  27                 d_done : in std_logic;
  28                 d_char : in hbyte
  29         );
  30 end entity pc_communication;
  31
  32 architecture beh of pc_communication is
  33         signal push_history, push_history_next : std_logic;
  34
  35         signal spalte, spalte_next : integer range 1 to hspalte_max + 1;
  36         signal zeile , zeile_next : integer range 1 to hzeile_max + 1;
  37         signal spalte_up, spalte_up_next : std_logic;
  38         signal get, get_next : std_logic;
  39         signal new_i, new_i_next : std_logic;
  40         signal tx_done_i, tx_done_i_next : std_logic;
  41         signal d_done_i : std_logic;
  42         signal s_done, s_done_next : std_logic;
  43
  44         signal char, char_next : hbyte;
  45         signal char_en : std_logic;
  46         type STATE_PC is (IDLE, FETCH, FORWARD, DONE);
  47         signal state, state_next : STATE_PC ;
  48
  49 begin
  50
  51
  52         d_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
  53         d_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
  54         d_get <= get;
  55         char_next <= d_char;
  56         tx_new <= new_i;
  57         d_done_i <= d_done;
  58         tx_done_i_next <= tx_done;
  59
  60         sync: process (sys_clk, sys_res_n)
  61         begin
  62                 if sys_res_n = '0' then
  63                         state <= IDLE;
  64                         push_history <= '0';
  65                         spalte <= 1;
  66                         zeile <= 1;
  67                         get <= '0';
  68                         new_i <= '0';
  69                         tx_data <= "00000000";
  70                         spalte_up <= '0';
  71                         tx_done_i <= '0';
  72                         s_done <= '0';
  73                 elsif rising_edge(sys_clk) then
  74                         push_history <= push_history_next;
  75                         spalte <= spalte_next;
  76                         zeile <= zeile_next;
  77                         state <= state_next;
  78                         get <= get_next;
  79                         new_i <= new_i_next;
  80                         tx_done_i <= tx_done_i_next;
  81                         spalte_up <= spalte_up_next;
  82                         s_done <= s_done_next;
  83                         if (char_en = '1') then
  84                                 char <= char_next;
  85                         end if;
  86                 end if;
  87         end process sync;
  88
  89         async_push_history : process (rx_new, rx_data, btn_a)
  90         begin
  91                 if rx_new = '1' then
  92                         if rx_data = X"41" then
  93                                 push_history_next <= '1';
  94                         else
  95                                 push_history_next <= '0';
  96                         end if;
  97                 elsif btn_a = '1' then
  98                                 push_history_next <= '1';
  99                 else
 100                         push_history_next <= '0';
 101                 end if;
 102         end process async_push_history;
 103
 104         output_pc : process (state, zeile, spalte, char, tx_done_i, spalte_up)
 105         begin
 106                 get_next <= '0';
 107                 new_i_next <= '0';
 108
 109                 spalte_up_next <= '0';
 110                 s_done_next <= '0';
 111                 spalte_next <= spalte;
 112                 zeile_next <= zeile;
 113
 114                 if spalte_up = '1' then
 115                         if spalte = hspalte_max  then
 116                                 if zeile = hzeile_max then
 117                                         spalte_next <= 1;
 118                                         zeile_next <= 1;
 119                                         s_done_next <= '1';
 120                                 else
 121                                         spalte_next <= 1;
 122                                         zeile_next <= zeile + 1;
 123                                 end if;
 124                         else
 125                                 spalte_next <= spalte + 1; --overflow here!
 126                                 zeile_next <= zeile;
 127                         end if;
 128                 end if;
 129
 130                 case state is
 131                         when IDLE =>
 132                                 null;
 133                         when FETCH =>
 134                                 get_next <= '1';
 135                                 char_en <= '1';
 136                         when FORWARD =>
 137                                 char_en <= '0';
 138                                 tx_data <= char;
 139                                 new_i_next <= '1';
 140                                 if (tx_done_i = '1') then
 141                                         spalte_up_next <= '1';
 142                                 end if;
 143
 144                         when DONE =>
 145                                 null;
 146                 end case;
 147         end process output_pc;
 148
 149         next_state_pc : process (rx_new, btn_a, d_done, tx_done_i, s_done)
 150         begin
 151                 case state is
 152                         when IDLE =>
 153                                 if rx_new = '1' or btn_a = '1' then
 154                                         state_next <= FETCH;
 155                                 end if;
 156                         when FETCH =>
 157                                 if (d_done = '1') then
 158                                         state_next <= FORWARD;
 159                                 elsif (s_done = '1') then
 160                                         state_next <= IDLE;
 161                                 end if;
 162                         when FORWARD =>
 163                                 if (tx_done_i = '1') then
 164                                         state_next <= FETCH;
 165                                 end if;
 166                         when DONE =>
 167                                 state_next <= IDLE;
 168                 end case;
 169         end process next_state_pc;
 170
 171 end architecture beh;