2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
6 entity pc_communication is
8 sys_clk : in std_logic;
9 sys_res_n : in std_logic;
13 tx_data : out std_logic_vector(7 downto 0);
14 tx_new : out std_logic;
15 tx_done : in std_logic;
17 rx_data : in std_logic_vector(7 downto 0);
18 rx_new : in std_logic;
20 pc_zeile : out hzeile;
21 pc_spalte : out hspalte;
22 pc_get : out std_logic;
23 pc_done : in std_logic;
26 end entity pc_communication;
28 architecture beh of pc_communication is
29 signal spalte, spalte_next : integer range 1 to HSPALTE_MAX + 2;
30 signal zeile , zeile_next : integer range 0 to HZEILE_MAX + 1;
31 signal get, get_next : std_logic;
32 signal new_i, new_i_next : std_logic;
33 signal tx_done_i, tx_done_i_next : std_logic;
34 signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0);
36 type STATE_PC is (IDLE, FETCH, FORWARD, UART_DONE, CR, CR_WAIT,
37 NL, NL_WAIT, PRINT_NO1, PRINT_NO1_WAIT, PRINT_NO2, PRINT_NO2_WAIT,
38 PRINT_NO3, PRINT_NO3_WAIT, PRINT_NO4, PRINT_NO4_WAIT, PRINT_NO5,
39 PRINT_NO5_WAIT, PRINT_NO6);
40 signal state, state_next : STATE_PC ;
42 pc_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
43 pc_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
46 tx_done_i_next <= tx_done;
49 sync: process (sys_clk, sys_res_n)
51 if sys_res_n = '0' then
59 elsif rising_edge(sys_clk) then
60 spalte <= spalte_next;
65 tx_done_i <= tx_done_i_next;
66 tx_data_i <= tx_data_i_next;
70 process (state, zeile, spalte, tx_data_i, tx_done_i, pc_char, rx_new, btn_a,
72 variable tmp : std_logic_vector(6 downto 0);
76 spalte_next <= spalte;
78 tx_data_i_next <= tx_data_i;
83 --if (rx_new = '1' and rx_data = x"0a") or btn_a = '0' then
84 if (rx_new = '1' or btn_a = '0') and tx_done_i = '0' then
85 state_next <= PRINT_NO1;
89 tx_data_i_next <= x"28"; -- '('
91 if tx_done_i = '1' then
92 state_next <= PRINT_NO1_WAIT;
94 when PRINT_NO1_WAIT =>
95 if tx_done_i = '0' then
96 state_next <= PRINT_NO2;
99 tx_data_i_next <= zeile2char(std_logic_vector(to_unsigned(zeile,7)), 1);
101 if tx_done_i = '1' then
102 state_next <= PRINT_NO2_WAIT;
104 when PRINT_NO2_WAIT =>
105 if tx_done_i = '0' then
106 state_next <= PRINT_NO3;
109 tx_data_i_next <= zeile2char(std_logic_vector(to_unsigned(zeile,7)), 2);
111 if tx_done_i = '1' then
112 state_next <= PRINT_NO3_WAIT;
114 when PRINT_NO3_WAIT =>
115 if tx_done_i = '0' then
116 state_next <= PRINT_NO4;
119 tx_data_i_next <= x"29"; -- ')'
121 if tx_done_i = '1' then
122 state_next <= PRINT_NO4_WAIT;
124 when PRINT_NO4_WAIT =>
125 if tx_done_i = '0' then
126 state_next <= PRINT_NO5;
129 tx_data_i_next <= x"24"; -- '$'
131 if tx_done_i = '1' then
132 state_next <= PRINT_NO5_WAIT;
134 when PRINT_NO5_WAIT =>
135 if tx_done_i = '0' then
136 state_next <= PRINT_NO6;
139 tx_data_i_next <= x"20"; -- ' '
141 if tx_done_i = '1' then
147 if pc_done = '1' and tx_done_i = '0' then
148 state_next <= FORWARD;
149 if pc_char = x"00" then
150 state_next <= UART_DONE;
154 tx_data_i_next <= pc_char;
156 -- halte pc_get weiterhin high sodass pc_char garantiert
157 -- gleicht bleibt (blockiert history!)
159 if tx_done_i = '1' then
160 state_next <= UART_DONE;
163 if tx_done_i = '0' then
165 spalte_next <= spalte + 1;
166 if spalte = HSPALTE_MAX + 1 then
169 zeile_next <= zeile + 1;
173 tx_data_i_next <= x"0a";
175 if tx_done_i = '1' then
176 state_next <= NL_WAIT;
179 if tx_done_i = '0' then
183 tx_data_i_next <= x"0d";
185 if tx_done_i = '1' then
186 state_next <= CR_WAIT;
189 if tx_done_i = '0' then
190 tmp := std_logic_vector(to_unsigned(zeile,7));
192 -- es handelt sich um eingabe im naechsten schritt
193 -- => print zeilennummer
194 state_next <= PRINT_NO1;
199 if zeile = HZEILE_MAX then
206 end architecture beh;