parser: erste gehversuche. im moment wird die eingabe einfach zurueckgegeben zur...
[hwmod.git] / src / parser.vhd
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4 use work.gen_pkg.all;
5
6 entity parser is
7         port
8         (
9                 sys_clk : in std_logic;
10                 sys_res_n : in std_logic;
11                 -- History
12                 p_rw : out std_logic;
13                 p_spalte : out hspalte;
14                 p_rget : out std_logic;
15                 p_rdone : in std_logic;
16                 p_read : in hbyte;
17                 p_wtake : out std_logic;
18                 p_wdone : in std_logic;
19                 p_write : out hbyte;
20                 p_finished : out std_logic;
21                 -- ALU
22                 opcode : out alu_ops;
23                 op1 : out csigned;
24                 op2 : out csigned;
25                 op3 : in csigned;
26                 do_calc : out std_logic;
27                 calc_done : in std_logic;
28                 -- TODO: calc_error : in std_logic;
29                 -- Scanner
30                 do_it : in std_logic;
31                 finished : out std_logic
32         );
33 end entity parser;
34
35 architecture beh of parser is
36         type PARSER_STATE is (SIDLE, SREAD_CHAR1, SREAD_CHAR2, SWRITE_CHAR);
37         signal state_int, state_next : PARSER_STATE;
38         signal z_int, z_next : csigned;
39         signal rbyte_int, rbyte_next : hbyte;
40         signal p_write_int, p_write_next : hbyte;
41         signal p_rget_int, p_rget_next : std_logic;
42         signal p_wtake_int, p_wtake_next : std_logic;
43         signal p_finished_int, p_finished_next : std_logic;
44 begin
45         p_write <= p_write_int;
46         p_rget <= p_rget_int;
47         p_wtake <= p_wtake_int;
48         p_finished <= p_finished_int;
49
50         process(sys_clk, sys_res_n)
51         begin
52                 if sys_res_n = '0' then
53                         state_int <= SIDLE;
54                         z_int <= (others => '0');
55                         rbyte_int <= (others => '0');
56                         -- out ports
57                         p_rw <= '0';
58                         p_spalte <= (others => '0');
59                         p_rget_int <= '0';
60                         p_write_int <= (others => '0');
61                         p_wtake_int <= '0';
62                         p_finished_int <= '0';
63                         opcode <= ALU_NOP;
64                         op1 <= (others => '0');
65                         op2 <= (others => '0');
66                         do_calc <= '0';
67                         finished <= '0';
68                 elsif rising_edge(sys_clk) then
69                         -- internal
70                         state_int <= state_next;
71                         z_int <= z_next;
72                         rbyte_int <= rbyte_next;
73                         -- out ports
74                         p_rget_int <= p_rget_next;
75                         p_write_int <= p_write_next;
76                         p_wtake_int <= p_wtake_next;
77                         p_finished_int <= p_finished_next;
78                 end if;
79         end process;
80
81         -- next state
82         process(state_int, do_it, p_rdone, p_wdone, p_read)
83         begin
84                 state_next <= state_int;
85
86                 case state_int is
87                         when SIDLE =>
88                                 if do_it = '1' then
89                                         state_next <= SREAD_CHAR1;
90                                 end if;
91                         when SREAD_CHAR1 =>
92                                 if p_rdone = '1' then
93                                         state_next <= SREAD_CHAR2;
94                                 end if;
95                         when SREAD_CHAR2 =>
96                                 if p_wdone = '1' then
97                                         state_next <= SWRITE_CHAR;
98                                 end if;
99                         when SWRITE_CHAR =>
100                                 if rbyte_int = hbyte(to_unsigned(character'pos(character'val(0)), 8)) then
101                                         if do_it = '0' then
102                                                 state_next <= SIDLE;
103                                         end if;
104                                 else
105                                         state_next <= SREAD_CHAR1;
106                                 end if;
107                 end case;
108         end process;
109
110         process(state_int, p_read, p_write_int, z_int, rbyte_int, p_rget_int)
111         begin
112                 -- internal
113                 z_next <= z_int;
114                 rbyte_next <= rbyte_int;
115                 -- signals
116                 p_rget_next <= '0';
117                 p_write_next <= p_write_int;
118                 p_wtake_next <= '0';
119                 p_finished_next <= '0';
120
121                 case state_int is
122                         when SIDLE =>
123                                 z_next <= (others => '0');
124                                 rbyte_next <= (others => '0');
125                                 p_write_next <= (others => '0');
126                         when SREAD_CHAR1 =>
127                                 p_rget_next <= '1';
128                                 p_write_next <= (others => '0');
129                         when SREAD_CHAR2 =>
130                                 rbyte_next <= p_read;
131                                 p_wtake_next <= '1';
132                                 p_write_next <= p_read;
133                         when SWRITE_CHAR =>
134                                 if rbyte_int = hbyte(to_unsigned(character'pos(character'val(0)), 8)) then
135                                         p_finished_next <= '1';
136                                 end if;
137                 end case;
138         end process;
139 end architecture beh;