src/history.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use work.gen_pkg.all;
   5
   6 entity history is
   7         port (
   8                 sys_clk : in std_logic;
   9                 sys_res_n : in std_logic;
  10                 -- PC-komm
  11                 -- TODO: pins
  12                 -- Scanner
  13                 s_char : in hbyte;
  14                 s_take : in std_logic;
  15                 s_done : out std_logic;
  16                 s_backspace : in std_logic;
  17                 -- Display
  18                 d_new_eingabe : out std_logic;
  19                 d_new_result : out std_logic;
  20                 d_new_bs : out std_logic;
  21                 d_zeile : in hzeile;
  22                 d_spalte : in hspalte;
  23                 d_get : in std_logic;
  24                 d_done : out std_logic;
  25                 d_char : out hbyte;
  26                 -- Parser
  27                 p_rget : in std_logic;
  28                 p_rdone : out std_logic;
  29                 p_read : out hbyte;
  30                 p_wtake : in std_logic;
  31                 p_wdone : out std_logic;
  32                 p_write : in hbyte;
  33                 p_finished : in std_logic
  34         );
  35 end entity history;
  36
  37 architecture beh of history is
  38         type HISTORY_STATE is (SIDLE, S_S_INIT, S_S_WRITE, S_S_BS, S_S_DONE, S_S_FIN,
  39                 S_D_INIT, S_D_READ, S_S_FIN_POSUP, S_P_READ, S_P_READ_DONE, S_P_WRITE,
  40                 S_P_WRITE_DONE, S_P_DONE, S_INIT, S_S_CLEAR_NEXT0, S_S_CLEAR_NEXT1);
  41         signal state_int, state_next : HISTORY_STATE;
  42         signal was_bs_int, was_bs_next : std_logic;
  43         signal pos_int, pos_next : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
  44         signal s_done_int, s_done_next : std_logic;
  45         signal s_cnt_int, s_cnt_next : hspalte;
  46         signal d_new_eingabe_int, d_new_eingabe_next : std_logic;
  47         signal d_new_result_int, d_new_result_next : std_logic;
  48         signal d_new_bs_int, d_new_bs_next: std_logic;
  49         signal d_done_int, d_done_next : std_logic;
  50         signal d_char_int, d_char_next : hbyte;
  51         signal p_rdone_int, p_rdone_next : std_logic;
  52         signal p_wdone_int, p_wdone_next : std_logic;
  53         signal p_read_int, p_read_next : hbyte;
  54         signal p_sp_read_int, p_sp_read_next : hspalte;
  55         signal p_sp_write_int, p_sp_write_next : hspalte;
  56
  57         -- ram
  58         signal address_next, address_int : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
  59         signal data_out, data_in_next, data_in_int : hbyte;
  60         signal wr_next, wr_int : std_logic;
  61 begin
  62         s_done <= s_done_int;
  63         d_new_eingabe <= d_new_eingabe_int;
  64         d_new_result <= d_new_result_int;
  65         d_new_bs <= d_new_bs_int;
  66         d_done <= d_done_int;
  67         d_char <= d_char_int;
  68         p_rdone <= p_rdone_int;
  69         p_wdone <= p_wdone_int;
  70         p_read <= p_read_int;
  71
  72         process(sys_clk, sys_res_n)
  73         begin
  74                 if sys_res_n = '0' then
  75                         -- internal
  76                         state_int <= S_INIT;
  77                         was_bs_int <= '0';
  78                         pos_int <= (others => '0');
  79                         -- out
  80                         s_done_int <= '0';
  81                         s_cnt_int <= (0 => '1', others => '0');
  82                         d_new_result_int <= '0';
  83                         d_new_eingabe_int <= '0';
  84                         d_new_bs_int <= '0';
  85                         d_done_int <= '0';
  86                         d_char_int <= (others => '0');
  87                         p_rdone_int <= '0';
  88                         p_wdone_int <= '0';
  89                         p_read_int <= (others => '0');
  90                         p_sp_read_int <= (others => '0');
  91                         p_sp_write_int <= std_logic_vector(to_unsigned(71,p_sp_write_int'length));
  92
  93                         address_int <= (0 => '1', others => '0');
  94                         data_in_int <= x"00";
  95                         wr_int <= '0';
  96                 elsif rising_edge(sys_clk) then
  97                         -- internal
  98                         state_int <= state_next;
  99                         was_bs_int <= was_bs_next;
 100                         pos_int <= pos_next;
 101                         -- out
 102                         s_done_int <= s_done_next;
 103                         s_cnt_int <= s_cnt_next;
 104                         d_new_result_int <= d_new_result_next;
 105                         d_new_eingabe_int <= d_new_eingabe_next;
 106                         d_new_bs_int <= d_new_bs_next;
 107                         d_done_int <= d_done_next;
 108                         d_char_int <= d_char_next;
 109                         p_rdone_int <= p_rdone_next;
 110                         p_wdone_int <= p_wdone_next;
 111                         p_read_int <= p_read_next;
 112                         p_sp_read_int <= p_sp_read_next;
 113                         p_sp_write_int <= p_sp_write_next;
 114
 115                         address_int <= address_next;
 116                         data_in_int <= data_in_next;
 117                         wr_int <= wr_next;
 118                 end if;
 119         end process;
 120
 121         -- next state
 122         process(state_int, d_get, p_finished, s_take, s_backspace, was_bs_int,
 123                 p_rget, p_wtake, pos_int, s_cnt_int)
 124         begin
 125                 state_next <= state_int;
 126
 127                 case state_int is
 128                         when S_INIT =>
 129                                 -- ganzen speicher clearen: fuer ausgabe am vga nicht umbedingt
 130                                 -- noetig, aber spaetestens fuers dumpen per rs232
 131                                 if pos_int = std_logic_vector(to_unsigned(H_RAM_SIZE,H_RAM_WIDTH)) then
 132                                         state_next <= SIDLE;
 133                                 end if;
 134                         when SIDLE =>
 135                                 -- S_S_FIN: tmp..
 136                                 if s_take = '1' then
 137                                         state_next <= S_S_INIT;
 138                                 elsif p_rget = '1' then
 139                                         state_next <= S_P_READ;
 140                                 elsif p_wtake = '1' then
 141                                         state_next <= S_P_WRITE;
 142                                 elsif p_finished = '1' then
 143                                         state_next <= S_S_FIN;
 144                                 elsif d_get = '1' then
 145                                         state_next <= S_D_INIT;
 146                                 end if;
 147                         when S_S_INIT =>
 148                                 if s_backspace = '1' then
 149                                         state_next <= S_S_BS;
 150                                 else
 151                                         state_next <= S_S_WRITE;
 152                                 end if;
 153                         when S_S_WRITE =>
 154                                 state_next <= S_S_DONE;
 155                         when S_S_BS =>
 156                                 state_next <= S_S_DONE;
 157                         when S_S_FIN =>
 158                                 if p_finished = '0' then
 159                                         state_next <= S_S_FIN_POSUP;
 160                                 end if;
 161                         when S_S_FIN_POSUP =>
 162                                 state_next <= S_S_CLEAR_NEXT0;
 163                         when S_S_CLEAR_NEXT0 =>
 164                                 if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then
 165                                         state_next <= S_S_CLEAR_NEXT1;
 166                                 end if;
 167                         when S_S_CLEAR_NEXT1 =>
 168                                 if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then
 169                                         state_next <= SIDLE;
 170                                 end if;
 171                         when S_S_DONE =>
 172                                 if s_take = '0' then
 173                                         state_next <= SIDLE;
 174                                 end if;
 175
 176                         when S_D_INIT =>
 177                                 state_next <= S_D_READ;
 178                         when S_D_READ =>
 179                                 if d_get = '0' then
 180                                         state_next <= SIDLE;
 181                                 end if;
 182
 183                         when S_P_READ =>
 184                                 state_next <= S_P_READ_DONE;
 185                         when S_P_READ_DONE =>
 186                                 if p_rget = '0' then
 187                                         state_next <= S_P_DONE;
 188                                 end if;
 189                         when S_P_WRITE =>
 190                                 state_next <= S_P_WRITE_DONE;
 191                         when S_P_WRITE_DONE =>
 192                                 if p_wtake = '0' then
 193                                         state_next <= S_P_DONE;
 194                                 end if;
 195                         when S_P_DONE =>
 196                                 state_next <= SIDLE;
 197                 end case;
 198         end process;
 199
 200         -- out
 201         process(state_int, s_cnt_int, d_spalte, d_zeile, data_out, s_char, address_int,
 202                         data_in_int, d_new_result_int, d_new_eingabe_int, d_new_bs_int,
 203                         was_bs_int, s_take, pos_int, p_rdone_int, p_wdone_int, p_read_int,
 204                         p_write, p_sp_read_int, p_sp_write_int)
 205                 variable addr_tmp : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
 206                 variable spalte_tmp : hspalte;
 207                 variable mul_tmp : std_logic_vector((H_RAM_WIDTH*2) -1 downto 0);
 208         begin
 209                 s_done_next <= '0';
 210                 s_cnt_next <= s_cnt_int;
 211                 was_bs_next <= was_bs_int;
 212                 pos_next <= pos_int;
 213                 d_new_result_next <= d_new_result_int;
 214                 d_new_eingabe_next <= d_new_eingabe_int;
 215                 d_new_bs_next <= '0';
 216                 d_done_next <= '0';
 217                 d_char_next <= (others => '0');
 218                 wr_next <= '0';
 219                 address_next <= address_int;
 220                 data_in_next <= data_in_int;
 221                 p_rdone_next <= p_rdone_int;
 222                 p_wdone_next <= p_wdone_int;
 223                 p_read_next <= p_read_int;
 224                 p_sp_read_next <= p_sp_read_int;
 225                 p_sp_write_next <= p_sp_write_int;
 226
 227                 case state_int is
 228                         when S_INIT =>
 229                                 wr_next <= '1';
 230                                 address_next <= pos_int;
 231                                 data_in_next <= (others => '0');
 232                                 if pos_int = std_logic_vector(to_unsigned(H_RAM_SIZE,H_RAM_WIDTH)) then
 233                                         pos_next <= (others => '0');
 234                                 else
 235                                         pos_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(1,H_RAM_WIDTH));
 236                                 end if;
 237                         when SIDLE =>
 238                                 d_new_result_next <= '0';
 239                         when S_S_INIT =>
 240                                 null;
 241                         when S_S_WRITE =>
 242                                 -- nur bei < 71 weiter machen
 243                                 -- Hint: '/=' billiger als '<'
 244                                 if unsigned(s_cnt_int) /= 71 then
 245                                         wr_next <= '1';
 246                                         address_next <= std_logic_vector(unsigned(pos_int) + unsigned(s_cnt_int));
 247                                         data_in_next <= s_char;
 248                                         s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1);
 249                                 else
 250                                         -- was_bs hier missbrauchen, um ein d_new_eingabe zu verhindern
 251                                         was_bs_next <= '1';
 252                                 end if;
 253                         when S_S_BS =>
 254                                 -- ab 1 darf nicht mehr dekrementiert werden
 255                                 addr_tmp := (others => '0');
 256                                 if unsigned(s_cnt_int) /= 1 then
 257                                         addr_tmp(hspalte'length - 1 downto 0) := std_logic_vector(unsigned(s_cnt_int) - 1);
 258                                         d_new_bs_next <= '1';
 259                                 else
 260                                         addr_tmp(hspalte'length - 1 downto 0) := s_cnt_int;
 261                                 end if;
 262                                 s_cnt_next <= addr_tmp(hspalte'length - 1 downto 0);
 263
 264                                 wr_next <= '1';
 265                                 address_next <= std_logic_vector(unsigned(pos_int) + unsigned(addr_tmp));
 266                                 data_in_next <= (others => '0');
 267                                 was_bs_next <= '1';
 268                         when S_S_FIN =>
 269                                 s_cnt_next <= (0 => '1', others => '0');
 270                                 d_new_result_next <= '1';
 271                                 -- resetten der parser counter
 272                                 p_sp_read_next <= (others => '0');
 273                                 p_sp_write_next <= std_logic_vector(to_unsigned(71,p_sp_write_next'length));
 274                         when S_S_FIN_POSUP =>
 275                                 -- overflowcheck nach 50 berechnungen => wieder von vorne anfangen
 276                                 if pos_int = std_logic_vector(to_unsigned(H_RAM_SIZE-142,H_RAM_WIDTH)) then
 277                                         pos_next <= (others => '0');
 278                                 else
 279                                         pos_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(142,H_RAM_WIDTH));
 280                                 end if;
 281                         when S_S_CLEAR_NEXT0 =>
 282                                 -- die naechsten 142 bytes im speicher resetten
 283                                 wr_next <= '1';
 284                                 address_next <= std_logic_vector(unsigned(pos_int) + unsigned(s_cnt_int));
 285                                 data_in_next <= (others => '0');
 286                                 if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then
 287                                         s_cnt_next <= (0 => '1', others => '0');
 288                                 else
 289                                         s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1);
 290                                 end if;
 291                         when S_S_CLEAR_NEXT1 =>
 292                                 -- die naechsten 142 bytes im speicher resetten
 293                                 wr_next <= '1';
 294                                 address_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(71,H_RAM_WIDTH) + unsigned(s_cnt_int));
 295                                 data_in_next <= (others => '0');
 296                                 if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then
 297                                         s_cnt_next <= (0 => '1', others => '0');
 298                                 else
 299                                         s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1);
 300                                 end if;
 301                         when S_S_DONE =>
 302                                 s_done_next <= '1';
 303                                 if was_bs_int = '0' then
 304                                         d_new_eingabe_next <= '1';
 305                                 end if;
 306                                 if s_take = '0' then
 307                                         was_bs_next <= '0';
 308                                 end if;
 309
 310                         when S_D_INIT =>
 311                                 addr_tmp := (others => '0');
 312                                 addr_tmp(hzeile'length - 1 downto 0) := d_zeile;
 313                                 mul_tmp := std_logic_vector(unsigned(addr_tmp) * to_unsigned(71,H_RAM_WIDTH));
 314                                 addr_tmp := mul_tmp((addr_tmp'length - 1) downto 0);
 315                                 addr_tmp := std_logic_vector(unsigned(addr_tmp) + unsigned(d_spalte));
 316                                 address_next <= addr_tmp;
 317                                 d_new_eingabe_next <= '0';
 318                                 d_new_result_next <= '0';
 319                         when S_D_READ =>
 320                                 d_char_next <= data_out;
 321                                 d_done_next <= '1';
 322
 323                         when S_P_READ =>
 324                                 wr_next <= '0';
 325                                 spalte_tmp := std_logic_vector(unsigned(p_sp_read_int) + 1);
 326                                 p_sp_read_next <= spalte_tmp;
 327                                 address_next <= std_logic_vector(unsigned(pos_int) + unsigned(spalte_tmp));
 328                         when S_P_READ_DONE =>
 329                                 p_rdone_next <= '1';
 330                                 p_read_next <= data_out;
 331
 332                         when S_P_WRITE =>
 333                                 wr_next <= '1';
 334                                 data_in_next <= p_write;
 335                                 spalte_tmp := std_logic_vector(unsigned(p_sp_write_int) - 1);
 336                                 p_sp_write_next <= spalte_tmp;
 337                                 address_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(71,H_RAM_WIDTH) + unsigned(spalte_tmp));
 338                         when S_P_WRITE_DONE =>
 339                                 p_wdone_next <= '1';
 340                         when S_P_DONE =>
 341                                 p_rdone_next <= '0';
 342                                 p_wdone_next <= '0';
 343                 end case;
 344         end process;
 345
 346         sp_ram_inst : entity work.sp_ram(beh)
 347         generic map (
 348                 ADDR_WIDTH => H_RAM_WIDTH
 349         )
 350         port map (
 351                 sys_clk => sys_clk,
 352                 address => address_int,
 353                 data_out => data_out,
 354                 wr => wr_int,
 355                 data_in => data_in_int
 356         );
 357 end architecture beh;