2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
8 sys_clk : in std_logic;
9 sys_res_n : in std_logic;
14 s_take : in std_logic;
15 s_done : out std_logic;
16 s_backspace : in std_logic;
18 d_new_eingabe : out std_logic;
19 d_new_result : out std_logic;
20 d_new_bs : out std_logic;
22 d_spalte : in hspalte;
24 d_done : out std_logic;
27 p_rget : in std_logic;
28 p_rdone : out std_logic;
30 p_wtake : in std_logic;
31 p_wdone : out std_logic;
33 p_finished : in std_logic
37 architecture beh of history is
38 type HISTORY_STATE is (SIDLE, S_S_INIT, S_S_WRITE, S_S_BS, S_S_DONE, S_S_FIN,
39 S_D_INIT, S_D_READ, S_S_FIN_POSUP, S_P_READ, S_P_READ_DONE, S_P_WRITE,
40 S_P_WRITE_DONE, S_P_DONE);
41 signal state_int, state_next : HISTORY_STATE;
42 signal was_bs_int, was_bs_next : std_logic;
43 signal pos_int, pos_next : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
44 signal s_done_int, s_done_next : std_logic;
45 signal s_cnt_int, s_cnt_next : hspalte;
46 signal d_new_eingabe_int, d_new_eingabe_next : std_logic;
47 signal d_new_result_int, d_new_result_next : std_logic;
48 signal d_new_bs_int, d_new_bs_next: std_logic;
49 signal d_done_int, d_done_next : std_logic;
50 signal d_char_int, d_char_next : hbyte;
51 signal p_rdone_int, p_rdone_next : std_logic;
52 signal p_wdone_int, p_wdone_next : std_logic;
53 signal p_read_int, p_read_next : hbyte;
54 signal p_sp_read_int, p_sp_read_next : hspalte;
55 signal p_sp_write_int, p_sp_write_next : hspalte;
58 signal address_next, address_int : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
59 signal data_out, data_in_next, data_in_int : hbyte;
60 signal wr_next, wr_int : std_logic;
63 d_new_eingabe <= d_new_eingabe_int;
64 d_new_result <= d_new_result_int;
65 d_new_bs <= d_new_bs_int;
68 p_rdone <= p_rdone_int;
69 p_wdone <= p_wdone_int;
72 process(sys_clk, sys_res_n)
74 if sys_res_n = '0' then
78 pos_int <= (others => '0');
81 s_cnt_int <= (0 => '1', others => '0');
82 d_new_result_int <= '0';
83 d_new_eingabe_int <= '0';
86 d_char_int <= (others => '0');
89 p_read_int <= (others => '0');
90 p_sp_read_int <= (others => '0');
91 p_sp_write_int <= std_logic_vector(to_unsigned(71,p_sp_write_int'length));
93 address_int <= (0 => '1', others => '0');
96 elsif rising_edge(sys_clk) then
98 state_int <= state_next;
99 was_bs_int <= was_bs_next;
102 s_done_int <= s_done_next;
103 s_cnt_int <= s_cnt_next;
104 d_new_result_int <= d_new_result_next;
105 d_new_eingabe_int <= d_new_eingabe_next;
106 d_new_bs_int <= d_new_bs_next;
107 d_done_int <= d_done_next;
108 d_char_int <= d_char_next;
109 p_rdone_int <= p_rdone_next;
110 p_wdone_int <= p_wdone_next;
111 p_read_int <= p_read_next;
112 p_sp_read_int <= p_sp_read_next;
113 p_sp_write_int <= p_sp_write_next;
115 address_int <= address_next;
116 data_in_int <= data_in_next;
122 process(state_int, d_get, p_finished, s_take, s_backspace, was_bs_int,
125 state_next <= state_int;
131 state_next <= S_S_INIT;
132 elsif p_rget = '1' then
133 state_next <= S_P_READ;
134 elsif p_wtake = '1' then
135 state_next <= S_P_WRITE;
136 elsif p_finished = '1' then
137 state_next <= S_S_FIN;
138 elsif d_get = '1' then
139 state_next <= S_D_INIT;
142 if s_backspace = '1' then
143 state_next <= S_S_BS;
145 state_next <= S_S_WRITE;
148 state_next <= S_S_DONE;
150 state_next <= S_S_DONE;
152 if p_finished = '0' then
153 state_next <= S_S_FIN_POSUP;
155 when S_S_FIN_POSUP =>
163 state_next <= S_D_READ;
170 state_next <= S_P_READ_DONE;
171 when S_P_READ_DONE =>
173 state_next <= S_P_DONE;
176 state_next <= S_P_WRITE_DONE;
177 when S_P_WRITE_DONE =>
178 if p_wtake = '0' then
179 state_next <= S_P_DONE;
187 process(state_int, s_cnt_int, d_spalte, d_zeile, data_out, s_char, address_int,
188 data_in_int, d_new_result_int, d_new_eingabe_int, d_new_bs_int,
189 was_bs_int, s_take, pos_int, p_rdone_int, p_wdone_int, p_read_int,
190 p_write, p_sp_read_int, p_sp_write_int)
191 variable addr_tmp : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
192 variable spalte_tmp : hspalte;
193 variable mul_tmp : std_logic_vector((H_RAM_WIDTH*2) -1 downto 0);
196 s_cnt_next <= s_cnt_int;
197 was_bs_next <= was_bs_int;
199 d_new_result_next <= d_new_result_int;
200 d_new_eingabe_next <= d_new_eingabe_int;
201 d_new_bs_next <= '0';
203 d_char_next <= (others => '0');
205 address_next <= address_int;
206 data_in_next <= data_in_int;
207 p_rdone_next <= p_rdone_int;
208 p_wdone_next <= p_wdone_int;
209 p_read_next <= p_read_int;
210 p_sp_read_next <= p_sp_read_int;
211 p_sp_write_next <= p_sp_write_int;
216 d_new_result_next <= '0';
220 -- nur bei < 71 weiter machen
221 -- TODO: '/=' billiger als '<' ?
222 if unsigned(s_cnt_int) /= 71 then
224 address_next <= std_logic_vector(unsigned(pos_int) + unsigned(s_cnt_int));
225 data_in_next <= s_char;
226 s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1);
228 -- was_bs hier missbrauchen, um ein d_new_eingabe zu verhindern
232 -- ab 1 darf nicht mehr dekrementiert werden
233 addr_tmp := (others => '0');
234 if unsigned(s_cnt_int) /= 1 then
235 addr_tmp(hspalte'length - 1 downto 0) := std_logic_vector(unsigned(s_cnt_int) - 1);
236 d_new_bs_next <= '1';
238 addr_tmp(hspalte'length - 1 downto 0) := s_cnt_int;
240 s_cnt_next <= addr_tmp(hspalte'length - 1 downto 0);
243 address_next <= std_logic_vector(unsigned(pos_int) + unsigned(addr_tmp));
244 data_in_next <= (others => '0');
247 s_cnt_next <= (0 => '1', others => '0');
248 d_new_result_next <= '1';
249 -- resetten der parser counter
250 p_sp_read_next <= (others => '0');
251 p_sp_write_next <= std_logic_vector(to_unsigned(71,p_sp_write_next'length));
252 when S_S_FIN_POSUP =>
253 -- TODO: overflow nach 50 berechnungen... => wieder von vorne anfangen
254 pos_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(142,H_RAM_WIDTH));
257 if was_bs_int = '0' then
258 d_new_eingabe_next <= '1';
265 addr_tmp := (others => '0');
266 addr_tmp(hzeile'length - 1 downto 0) := d_zeile;
267 mul_tmp := std_logic_vector(unsigned(addr_tmp) * to_unsigned(71,H_RAM_WIDTH));
268 addr_tmp := mul_tmp((addr_tmp'length - 1) downto 0);
269 addr_tmp := std_logic_vector(unsigned(addr_tmp) + unsigned(d_spalte));
270 address_next <= addr_tmp;
271 d_new_eingabe_next <= '0';
272 d_new_result_next <= '0';
274 d_char_next <= data_out;
279 spalte_tmp := std_logic_vector(unsigned(p_sp_read_int) + 1);
280 p_sp_read_next <= spalte_tmp;
281 address_next <= std_logic_vector(unsigned(pos_int) + unsigned(spalte_tmp));
282 when S_P_READ_DONE =>
284 p_read_next <= data_out;
288 data_in_next <= p_write;
289 spalte_tmp := std_logic_vector(unsigned(p_sp_write_int) - 1);
290 p_sp_write_next <= spalte_tmp;
291 address_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(71,H_RAM_WIDTH) + unsigned(spalte_tmp));
292 when S_P_WRITE_DONE =>
300 sp_ram_inst : entity work.sp_ram(beh)
302 ADDR_WIDTH => H_RAM_WIDTH
306 address => address_int,
307 data_out => data_out,
309 data_in => data_in_int
311 end architecture beh;