2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
8 sys_clk : in std_logic;
9 sys_res_n : in std_logic;
14 s_take : in std_logic;
15 s_done : out std_logic;
16 s_backspace : in std_logic;
18 d_new_eingabe : out std_logic;
19 d_new_result : out std_logic;
21 d_spalte : in hspalte;
23 d_done : out std_logic;
30 finished : out std_logic
34 architecture beh of history is
35 type HISTORY_STATE is (SIDLE, S_S_INIT, S_S_WRITE, S_S_BS, S_S_DONE, S_S_FIN,
36 S_D_INIT, S_D_WAIT, S_D_WRITE);
37 signal state_int, state_next : HISTORY_STATE;
38 signal s_done_int, s_done_next : std_logic;
39 signal s_cnt_int, s_cnt_next : hspalte;
40 signal d_new_eingabe_int, d_new_eingabe_next : std_logic;
41 signal d_new_result_int, d_new_result_next : std_logic;
42 signal d_done_int, d_done_next : std_logic;
43 signal d_char_int, d_char_next : hbyte;
45 signal finished_int, finished_next : std_logic;
48 signal address_next, address_int : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
49 signal data_out, data_in_next, data_in_int : hbyte;
50 signal wr_next, wr_int : std_logic;
53 d_new_eingabe <= d_new_eingabe_int;
54 d_new_result <= d_new_result_int;
58 finished <= finished_int;
60 process(sys_clk, sys_res_n)
62 if sys_res_n = '0' then
67 s_cnt_int <= (0 => '1', others => '0');
68 d_new_result_int <= '0';
69 d_new_eingabe_int <= '0';
71 d_char_int <= (others => '0');
75 address_int <= (0 => '1', others => '0');
78 elsif rising_edge(sys_clk) then
80 state_int <= state_next;
82 s_done_int <= s_done_next;
83 s_cnt_int <= s_cnt_next;
84 d_new_result_int <= d_new_result_next;
85 d_new_eingabe_int <= d_new_eingabe_next;
86 d_done_int <= d_done_next;
87 d_char_int <= d_char_next;
89 finished_int <= finished_next;
91 address_int <= address_next;
92 data_in_int <= data_in_next;
98 process(state_int, d_get, do_it, s_take, s_backspace)
100 state_next <= state_int;
106 state_next <= S_S_INIT;
107 elsif do_it = '1' then
108 state_next <= S_S_FIN;
109 elsif d_get = '1' then
110 state_next <= S_D_INIT;
113 if s_backspace = '1' then
114 state_next <= S_S_BS;
116 state_next <= S_S_WRITE;
118 when S_S_WRITE | S_S_BS =>
119 state_next <= S_S_DONE;
130 state_next <= S_D_WAIT;
132 state_next <= S_D_WRITE;
141 process(state_int, s_cnt_int, d_spalte, data_out, s_char, address_int,
142 data_in_int, d_new_result_int, d_new_eingabe_int)
145 s_cnt_next <= s_cnt_int;
146 d_new_result_next <= d_new_result_int;
147 d_new_eingabe_next <= d_new_eingabe_int;
149 d_char_next <= (others => '0');
150 finished_next <= '0';
152 address_next <= address_int;
153 data_in_next <= data_in_int;
160 d_new_result_next <= '0';
163 address_next <= s_cnt_int;
164 data_in_next <= s_char;
165 s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1);
168 address_next <= std_logic_vector(unsigned(s_cnt_int) - 1);
169 data_in_next <= (others => '0');
170 if unsigned(s_cnt_int) /= 0 then
171 s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) - 1);
174 finished_next <= '1';
175 s_cnt_next <= (0 => '1', others => '0');
176 d_new_result_next <= '1';
179 d_new_eingabe_next <= '1';
182 address_next <= d_spalte;
183 d_new_eingabe_next <= '0';
184 d_new_result_next <= '0';
188 d_char_next <= data_out;
193 sp_ram_inst : entity work.sp_ram(beh)
195 ADDR_WIDTH => H_RAM_WIDTH
199 address => address_int,
200 data_out => data_out,
202 data_in => data_in_int
204 end architecture beh;