src/history.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use work.gen_pkg.all;
   5
   6 entity history is
   7         port (
   8                 sys_clk : in std_logic;
   9                 sys_res_n : in std_logic;
  10                 -- PC-komm
  11                 -- TODO: pins
  12                 -- Scanner
  13                 s_char : in hbyte;
  14                 s_take : in std_logic;
  15                 s_done : out std_logic;
  16                 s_backspace : in std_logic;
  17                 -- Display
  18                 d_new_eingabe : out std_logic;
  19                 d_new_result : out std_logic;
  20                 d_new_bs : out std_logic;
  21                 d_zeile : in hzeile;
  22                 d_spalte : in hspalte;
  23                 d_get : in std_logic;
  24                 d_done : out std_logic;
  25                 d_char : out hbyte;
  26                 -- Parser
  27                 p_rget : in std_logic;
  28                 p_rdone : out std_logic;
  29                 p_read : out hbyte;
  30                 p_wtake : in std_logic;
  31                 p_wdone : out std_logic;
  32                 p_write : in hbyte;
  33                 p_finished : in std_logic
  34         );
  35 end entity history;
  36
  37 architecture beh of history is
  38         type HISTORY_STATE is (SIDLE, S_S_INIT, S_S_WRITE, S_S_BS, S_S_DONE, S_S_FIN,
  39                 S_D_INIT, S_D_READ, S_S_FIN_POSUP, S_P_READ, S_P_READ_DONE, S_P_WRITE,
  40                 S_P_WRITE_DONE, S_P_DONE);
  41         signal state_int, state_next : HISTORY_STATE;
  42         signal was_bs_int, was_bs_next : std_logic;
  43         signal pos_int, pos_next : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
  44         signal s_done_int, s_done_next : std_logic;
  45         signal s_cnt_int, s_cnt_next : hspalte;
  46         signal d_new_eingabe_int, d_new_eingabe_next : std_logic;
  47         signal d_new_result_int, d_new_result_next : std_logic;
  48         signal d_new_bs_int, d_new_bs_next: std_logic;
  49         signal d_done_int, d_done_next : std_logic;
  50         signal d_char_int, d_char_next : hbyte;
  51         signal p_rdone_int, p_rdone_next : std_logic;
  52         signal p_wdone_int, p_wdone_next : std_logic;
  53         signal p_read_int, p_read_next : hbyte;
  54         signal p_sp_read_int, p_sp_read_next : hspalte;
  55         signal p_sp_write_int, p_sp_write_next : hspalte;
  56
  57         -- ram
  58         signal address_next, address_int : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
  59         signal data_out, data_in_next, data_in_int : hbyte;
  60         signal wr_next, wr_int : std_logic;
  61 begin
  62         s_done <= s_done_int;
  63         d_new_eingabe <= d_new_eingabe_int;
  64         d_new_result <= d_new_result_int;
  65         d_new_bs <= d_new_bs_int;
  66         d_done <= d_done_int;
  67         d_char <= d_char_int;
  68         p_rdone <= p_rdone_int;
  69         p_wdone <= p_wdone_int;
  70         p_read <= p_read_int;
  71
  72         process(sys_clk, sys_res_n)
  73         begin
  74                 if sys_res_n = '0' then
  75                         -- internal
  76                         state_int <= SIDLE;
  77                         was_bs_int <= '0';
  78                         pos_int <= (others => '0');
  79                         -- out
  80                         s_done_int <= '0';
  81                         s_cnt_int <= (0 => '1', others => '0');
  82                         d_new_result_int <= '0';
  83                         d_new_eingabe_int <= '0';
  84                         d_new_bs_int <= '0';
  85                         d_done_int <= '0';
  86                         d_char_int <= (others => '0');
  87                         p_rdone_int <= '0';
  88                         p_wdone_int <= '0';
  89                         p_read_int <= (others => '0');
  90                         p_sp_read_int <= (others => '0');
  91                         p_sp_write_int <= (others => '0');
  92
  93                         address_int <= (0 => '1', others => '0');
  94                         data_in_int <= x"00";
  95                         wr_int <= '0';
  96                 elsif rising_edge(sys_clk) then
  97                         -- internal
  98                         state_int <= state_next;
  99                         was_bs_int <= was_bs_next;
 100                         pos_int <= pos_next;
 101                         -- out
 102                         s_done_int <= s_done_next;
 103                         s_cnt_int <= s_cnt_next;
 104                         d_new_result_int <= d_new_result_next;
 105                         d_new_eingabe_int <= d_new_eingabe_next;
 106                         d_new_bs_int <= d_new_bs_next;
 107                         d_done_int <= d_done_next;
 108                         d_char_int <= d_char_next;
 109                         p_rdone_int <= p_rdone_next;
 110                         p_wdone_int <= p_wdone_next;
 111                         p_read_int <= p_read_next;
 112                         p_sp_read_int <= p_sp_read_next;
 113                         p_sp_write_int <= p_sp_write_next;
 114
 115                         address_int <= address_next;
 116                         data_in_int <= data_in_next;
 117                         wr_int <= wr_next;
 118                 end if;
 119         end process;
 120
 121         -- next state
 122         process(state_int, d_get, p_finished, s_take, s_backspace, was_bs_int,
 123                 p_rget, p_wtake)
 124         begin
 125                 state_next <= state_int;
 126
 127                 case state_int is
 128                         when SIDLE =>
 129                                 -- S_S_FIN: tmp..
 130                                 if s_take = '1' then
 131                                         state_next <= S_S_INIT;
 132                                 elsif p_rget = '1' then
 133                                         state_next <= S_P_READ;
 134                                 elsif p_wtake = '1' then
 135                                         state_next <= S_P_WRITE;
 136                                 elsif p_finished = '1' then
 137                                         state_next <= S_S_FIN;
 138                                 elsif d_get = '1' then
 139                                         state_next <= S_D_INIT;
 140                                 end if;
 141                         when S_S_INIT =>
 142                                 if s_backspace = '1' then
 143                                         state_next <= S_S_BS;
 144                                 else
 145                                         state_next <= S_S_WRITE;
 146                                 end if;
 147                         when S_S_WRITE =>
 148                                 state_next <= S_S_DONE;
 149                         when S_S_BS =>
 150                                 state_next <= S_S_DONE;
 151                         when S_S_FIN =>
 152                                 if p_finished = '0' then
 153                                         state_next <= S_S_FIN_POSUP;
 154                                 end if;
 155                         when S_S_FIN_POSUP =>
 156                                 state_next <= SIDLE;
 157                         when S_S_DONE =>
 158                                 if s_take = '0' then
 159                                         state_next <= SIDLE;
 160                                 end if;
 161
 162                         when S_D_INIT =>
 163                                 state_next <= S_D_READ;
 164                         when S_D_READ =>
 165                                 if d_get = '0' then
 166                                         state_next <= SIDLE;
 167                                 end if;
 168
 169                         when S_P_READ =>
 170                                 state_next <= S_P_READ_DONE;
 171                         when S_P_READ_DONE =>
 172                                 if p_rget = '0' then
 173                                         state_next <= S_P_DONE;
 174                                 end if;
 175                         when S_P_WRITE =>
 176                                 state_next <= S_P_WRITE_DONE;
 177                         when S_P_WRITE_DONE =>
 178                                 if p_wtake = '0' then
 179                                         state_next <= S_P_DONE;
 180                                 end if;
 181                         when S_P_DONE =>
 182                                 state_next <= SIDLE;
 183                 end case;
 184         end process;
 185
 186         -- out
 187         process(state_int, s_cnt_int, d_spalte, d_zeile, data_out, s_char, address_int,
 188                         data_in_int, d_new_result_int, d_new_eingabe_int, d_new_bs_int,
 189                         was_bs_int, s_take, pos_int, p_rdone_int, p_wdone_int, p_read_int,
 190                         p_write, p_sp_read_int, p_sp_write_int)
 191                 variable addr_tmp : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
 192                 variable spalte_tmp : hspalte;
 193                 variable mul_tmp : std_logic_vector((H_RAM_WIDTH*2) -1 downto 0);
 194         begin
 195                 s_done_next <= '0';
 196                 s_cnt_next <= s_cnt_int;
 197                 was_bs_next <= was_bs_int;
 198                 pos_next <= pos_int;
 199                 d_new_result_next <= d_new_result_int;
 200                 d_new_eingabe_next <= d_new_eingabe_int;
 201                 d_new_bs_next <= '0';
 202                 d_done_next <= '0';
 203                 d_char_next <= (others => '0');
 204                 wr_next <= '0';
 205                 address_next <= address_int;
 206                 data_in_next <= data_in_int;
 207                 p_rdone_next <= p_rdone_int;
 208                 p_wdone_next <= p_wdone_int;
 209                 p_read_next <= p_read_int;
 210                 p_sp_read_next <= p_sp_read_int;
 211                 p_sp_write_next <= p_sp_write_int;
 212
 213                 case state_int is
 214                         when SIDLE =>
 215                                 -- TODO: tmp fix
 216                                 d_new_result_next <= '0';
 217                         when S_S_INIT =>
 218                                 null;
 219                         when S_S_WRITE =>
 220                                 -- nur bei < 71 weiter machen
 221                                 -- TODO: '/=' billiger als '<' ?
 222                                 if unsigned(s_cnt_int) /= 71 then
 223                                         wr_next <= '1';
 224                                         address_next <= std_logic_vector(unsigned(pos_int) + unsigned(s_cnt_int));
 225                                         data_in_next <= s_char;
 226                                         s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1);
 227                                 else
 228                                         -- was_bs hier missbrauchen, um ein d_new_eingabe zu verhindern
 229                                         was_bs_next <= '1';
 230                                 end if;
 231                         when S_S_BS =>
 232                                 -- ab 1 darf nicht mehr dekrementiert werden
 233                                 addr_tmp := (others => '0');
 234                                 if unsigned(s_cnt_int) /= 1 then
 235                                         addr_tmp(hspalte'length - 1 downto 0) := std_logic_vector(unsigned(s_cnt_int) - 1);
 236                                         d_new_bs_next <= '1';
 237                                 else
 238                                         addr_tmp(hspalte'length - 1 downto 0) := s_cnt_int;
 239                                 end if;
 240                                 s_cnt_next <= addr_tmp(hspalte'length - 1 downto 0);
 241
 242                                 wr_next <= '1';
 243                                 address_next <= std_logic_vector(unsigned(pos_int) + unsigned(addr_tmp));
 244                                 data_in_next <= (others => '0');
 245                                 was_bs_next <= '1';
 246                         when S_S_FIN =>
 247                                 s_cnt_next <= (0 => '1', others => '0');
 248                                 d_new_result_next <= '1';
 249                         when S_S_FIN_POSUP =>
 250                                 -- TODO: overflow nach 50 berechnungen... => wieder von vorne anfangen
 251                                 pos_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(142,H_RAM_WIDTH));
 252                         when S_S_DONE =>
 253                                 s_done_next <= '1';
 254                                 if was_bs_int = '0' then
 255                                         d_new_eingabe_next <= '1';
 256                                 end if;
 257                                 if s_take = '0' then
 258                                         was_bs_next <= '0';
 259                                 end if;
 260                                 -- TODO: bessere stelle fuers reseten der parser signale?
 261                                 p_sp_read_next <= (others => '0');
 262                                 p_sp_write_next <= std_logic_vector(to_unsigned(71,p_sp_write_next'length));
 263
 264                         when S_D_INIT =>
 265                                 addr_tmp := (others => '0');
 266                                 addr_tmp(hzeile'length - 1 downto 0) := d_zeile;
 267                                 mul_tmp := std_logic_vector(unsigned(addr_tmp) * to_unsigned(71,H_RAM_WIDTH));
 268                                 addr_tmp := mul_tmp((addr_tmp'length - 1) downto 0);
 269                                 addr_tmp := std_logic_vector(unsigned(addr_tmp) + unsigned(d_spalte));
 270                                 address_next <= addr_tmp;
 271                                 d_new_eingabe_next <= '0';
 272                                 d_new_result_next <= '0';
 273                         when S_D_READ =>
 274                                 d_char_next <= data_out;
 275                                 d_done_next <= '1';
 276
 277                         when S_P_READ =>
 278                                 wr_next <= '0';
 279                                 spalte_tmp := std_logic_vector(unsigned(p_sp_read_int) + 1);
 280                                 p_sp_read_next <= spalte_tmp;
 281                                 address_next <= std_logic_vector(unsigned(pos_int) + unsigned(spalte_tmp));
 282                         when S_P_READ_DONE =>
 283                                 p_rdone_next <= '1';
 284                                 p_read_next <= data_out;
 285
 286                         when S_P_WRITE =>
 287                                 wr_next <= '1';
 288                                 data_in_next <= p_write;
 289                                 spalte_tmp := std_logic_vector(unsigned(p_sp_write_int) - 1);
 290                                 p_sp_write_next <= spalte_tmp;
 291                                 address_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(71,H_RAM_WIDTH) + unsigned(spalte_tmp));
 292                         when S_P_WRITE_DONE =>
 293                                 p_wdone_next <= '1';
 294                         when S_P_DONE =>
 295                                 p_rdone_next <= '0';
 296                                 p_wdone_next <= '0';
 297                 end case;
 298         end process;
 299
 300         sp_ram_inst : entity work.sp_ram(beh)
 301         generic map (
 302                 ADDR_WIDTH => H_RAM_WIDTH
 303         )
 304         port map (
 305                 sys_clk => sys_clk,
 306                 address => address_int,
 307                 data_out => data_out,
 308                 wr => wr_int,
 309                 data_in => data_in_int
 310         );
 311 end architecture beh;