src/history.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use work.gen_pkg.all;
   5
   6 entity history is
   7         port (
   8                 sys_clk : in std_logic;
   9                 sys_res_n : in std_logic;
  10                 -- PC-komm
  11                 pc_get :  in std_logic;
  12                 pc_spalte : in hspalte;
  13                 pc_zeile : in hzeile;
  14                 pc_char : out hbyte;
  15                 pc_done : out std_logic;
  16                 pc_busy : out std_logic;
  17                 -- Scanner
  18                 s_char : in hbyte;
  19                 s_take : in std_logic;
  20                 s_done : out std_logic;
  21                 s_backspace : in std_logic;
  22                 -- Display
  23                 d_new_eingabe : out std_logic;
  24                 d_new_result : out std_logic;
  25                 d_new_bs : out std_logic;
  26                 d_zeile : in hzeile;
  27                 d_spalte : in hspalte;
  28                 d_get : in std_logic;
  29                 d_done : out std_logic;
  30                 d_char : out hbyte;
  31                 -- Parser
  32                 p_rget : in std_logic;
  33                 p_rdone : out std_logic;
  34                 p_read : out hbyte;
  35                 p_wtake : in std_logic;
  36                 p_wdone : out std_logic;
  37                 p_write : in hbyte;
  38                 p_finished : in std_logic
  39         );
  40 end entity history;
  41
  42 architecture beh of history is
  43         type HISTORY_STATE is (SIDLE, S_S_INIT, S_S_WRITE, S_S_BS, S_S_DONE, S_S_FIN,
  44                 S_D_INIT, S_D_READ, S_S_FIN_POSUP, S_P_READ, S_P_READ_DONE, S_P_WRITE,
  45                 S_P_WRITE_DONE, S_P_DONE, S_INIT, S_S_CLEAR_NEXT0, S_S_CLEAR_NEXT1, S_PC_INIT, S_PC_READ);
  46         signal state_int, state_next : HISTORY_STATE;
  47         signal was_bs_int, was_bs_next : std_logic;
  48         signal pos_int, pos_next : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
  49         signal s_done_int, s_done_next : std_logic;
  50         signal s_cnt_int, s_cnt_next : hspalte;
  51         signal d_new_eingabe_int, d_new_eingabe_next : std_logic;
  52         signal d_new_result_int, d_new_result_next : std_logic;
  53         signal d_new_bs_int, d_new_bs_next: std_logic;
  54         signal d_done_int, d_done_next : std_logic;
  55         signal d_char_int, d_char_next : hbyte;
  56         signal p_rdone_int, p_rdone_next : std_logic;
  57         signal p_wdone_int, p_wdone_next : std_logic;
  58         signal p_read_int, p_read_next : hbyte;
  59         signal p_sp_read_int, p_sp_read_next : hspalte;
  60         signal p_sp_write_int, p_sp_write_next : hspalte;
  61         signal pc_char_next ,pc_char_int : hbyte;
  62         signal pc_done_next, pc_done_int : std_logic;
  63         signal pc_busy_next, pc_busy_int : std_logic;
  64
  65         -- ram
  66         signal address_next, address_int : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
  67         signal data_out, data_in_next, data_in_int : hbyte;
  68         signal wr_next, wr_int : std_logic;
  69 begin
  70         s_done <= s_done_int;
  71         d_new_eingabe <= d_new_eingabe_int;
  72         d_new_result <= d_new_result_int;
  73         d_new_bs <= d_new_bs_int;
  74         d_done <= d_done_int;
  75         d_char <= d_char_int;
  76         p_rdone <= p_rdone_int;
  77         p_wdone <= p_wdone_int;
  78         p_read <= p_read_int;
  79         pc_done <= pc_done_int;
  80         pc_busy <= pc_busy_int;
  81         pc_char <= pc_char_int;
  82
  83         process(sys_clk, sys_res_n)
  84         begin
  85                 if sys_res_n = '0' then
  86                         -- internal
  87                         state_int <= S_INIT;
  88                         was_bs_int <= '0';
  89                         pos_int <= (others => '0');
  90                         -- out
  91                         s_done_int <= '0';
  92                         s_cnt_int <= (0 => '1', others => '0');
  93                         d_new_result_int <= '0';
  94                         d_new_eingabe_int <= '0';
  95                         d_new_bs_int <= '0';
  96                         d_done_int <= '0';
  97                         d_char_int <= (others => '0');
  98                         p_rdone_int <= '0';
  99                         p_wdone_int <= '0';
 100                         p_read_int <= (others => '0');
 101                         p_sp_read_int <= (others => '0');
 102                         p_sp_write_int <= std_logic_vector(to_unsigned(71,p_sp_write_int'length));
 103
 104                         pc_char_int  <= (others => '0');
 105                         pc_done_int  <= '0';
 106                         pc_busy_int <= '0';
 107
 108                         address_int <= (0 => '1', others => '0');
 109                         data_in_int <= x"00";
 110                         wr_int <= '0';
 111                 elsif rising_edge(sys_clk) then
 112                         -- internal
 113                         state_int <= state_next;
 114                         was_bs_int <= was_bs_next;
 115                         pos_int <= pos_next;
 116                         -- out
 117                         s_done_int <= s_done_next;
 118                         s_cnt_int <= s_cnt_next;
 119                         d_new_result_int <= d_new_result_next;
 120                         d_new_eingabe_int <= d_new_eingabe_next;
 121                         d_new_bs_int <= d_new_bs_next;
 122                         d_done_int <= d_done_next;
 123                         d_char_int <= d_char_next;
 124                         p_rdone_int <= p_rdone_next;
 125                         p_wdone_int <= p_wdone_next;
 126                         p_read_int <= p_read_next;
 127                         p_sp_read_int <= p_sp_read_next;
 128                         p_sp_write_int <= p_sp_write_next;
 129
 130                         pc_char_int <= pc_char_next;
 131                         pc_done_int <= pc_done_next;
 132                         pc_busy_int <= pc_busy_next;
 133
 134                         address_int <= address_next;
 135                         data_in_int <= data_in_next;
 136                         wr_int <= wr_next;
 137                 end if;
 138         end process;
 139
 140         -- next state
 141         process(state_int, d_get, pc_get, p_finished, s_take, s_backspace, was_bs_int,
 142                 p_rget, p_wtake, pos_int, s_cnt_int)
 143         begin
 144                 state_next <= state_int;
 145
 146                 case state_int is
 147                         when S_INIT =>
 148                                 -- ganzen speicher clearen: fuer ausgabe am vga nicht umbedingt
 149                                 -- noetig, aber spaetestens fuers dumpen per rs232
 150                                 if pos_int = std_logic_vector(to_unsigned(H_RAM_SIZE,H_RAM_WIDTH)) then
 151                                         state_next <= SIDLE;
 152                                 end if;
 153                         when SIDLE =>
 154                                 -- S_S_FIN: tmp..
 155                                 if s_take = '1' then
 156                                         state_next <= S_S_INIT;
 157                                 elsif p_rget = '1' then
 158                                         state_next <= S_P_READ;
 159                                 elsif p_wtake = '1' then
 160                                         state_next <= S_P_WRITE;
 161                                 elsif p_finished = '1' then
 162                                         state_next <= S_S_FIN;
 163                                 elsif d_get = '1' then
 164                                         state_next <= S_D_INIT;
 165                                 elsif pc_get = '1' then
 166                                         state_next <= S_PC_INIT;
 167                                 end if;
 168                         when S_S_INIT =>
 169                                 if s_backspace = '1' then
 170                                         state_next <= S_S_BS;
 171                                 else
 172                                         state_next <= S_S_WRITE;
 173                                 end if;
 174                         when S_S_WRITE =>
 175                                 state_next <= S_S_DONE;
 176                         when S_S_BS =>
 177                                 state_next <= S_S_DONE;
 178                         when S_S_FIN =>
 179                                 if p_finished = '0' then
 180                                         state_next <= S_S_FIN_POSUP;
 181                                 end if;
 182                         when S_S_FIN_POSUP =>
 183                                 state_next <= S_S_CLEAR_NEXT0;
 184                         when S_S_CLEAR_NEXT0 =>
 185                                 if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then
 186                                         state_next <= S_S_CLEAR_NEXT1;
 187                                 end if;
 188                         when S_S_CLEAR_NEXT1 =>
 189                                 if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then
 190                                         state_next <= SIDLE;
 191                                 end if;
 192                         when S_S_DONE =>
 193                                 if s_take = '0' then
 194                                         state_next <= SIDLE;
 195                                 end if;
 196
 197                         when S_D_INIT =>
 198                                 state_next <= S_D_READ;
 199                         when S_D_READ =>
 200                                 if d_get = '0' then
 201                                         state_next <= SIDLE;
 202                                 end if;
 203                         when S_PC_INIT =>
 204                                 state_next <= S_PC_READ;
 205                         when S_PC_READ =>
 206                                 if d_get = '0' then
 207                                         state_next <= SIDLE;
 208                                 end if;
 209                         when S_P_READ =>
 210                                 state_next <= S_P_READ_DONE;
 211                         when S_P_READ_DONE =>
 212                                 if p_rget = '0' then
 213                                         state_next <= S_P_DONE;
 214                                 end if;
 215                         when S_P_WRITE =>
 216                                 state_next <= S_P_WRITE_DONE;
 217                         when S_P_WRITE_DONE =>
 218                                 if p_wtake = '0' then
 219                                         state_next <= S_P_DONE;
 220                                 end if;
 221                         when S_P_DONE =>
 222                                 state_next <= SIDLE;
 223                 end case;
 224         end process;
 225
 226         -- out
 227         process(state_int, s_cnt_int, d_spalte, d_zeile, data_out, s_char, address_int,
 228                         data_in_int, d_new_result_int, d_new_eingabe_int, d_new_bs_int,
 229                         was_bs_int, s_take, pos_int, p_rdone_int, p_wdone_int, p_read_int,
 230                         p_write, p_sp_read_int, p_sp_write_int, pc_char_int, pc_zeile, pc_spalte)
 231                 variable addr_tmp : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
 232                 variable spalte_tmp : hspalte;
 233                 variable mul_tmp : std_logic_vector((H_RAM_WIDTH*2) -1 downto 0);
 234         begin
 235                 s_done_next <= '0';
 236                 s_cnt_next <= s_cnt_int;
 237                 was_bs_next <= was_bs_int;
 238                 pos_next <= pos_int;
 239                 d_new_result_next <= d_new_result_int;
 240                 d_new_eingabe_next <= d_new_eingabe_int;
 241                 d_new_bs_next <= '0';
 242                 d_done_next <= '0';
 243                 d_char_next <= (others => '0');
 244                 wr_next <= '0';
 245                 address_next <= address_int;
 246                 data_in_next <= data_in_int;
 247                 pc_done_next <= '0';
 248                 pc_char_next <= pc_char_int; --(others => '0');
 249                 pc_busy_next <= '0';
 250                 p_rdone_next <= p_rdone_int;
 251                 p_wdone_next <= p_wdone_int;
 252                 p_read_next <= p_read_int;
 253                 p_sp_read_next <= p_sp_read_int;
 254                 p_sp_write_next <= p_sp_write_int;
 255
 256                 case state_int is
 257                         when S_INIT =>
 258                                 wr_next <= '1';
 259                                 address_next <= pos_int;
 260                                 data_in_next <= (others => '0');
 261                                 if pos_int = std_logic_vector(to_unsigned(H_RAM_SIZE,H_RAM_WIDTH)) then
 262                                         pos_next <= (others => '0');
 263                                 else
 264                                         pos_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(1,H_RAM_WIDTH));
 265                                 end if;
 266                         when SIDLE =>
 267                                 d_new_result_next <= '0';
 268                         when S_S_INIT =>
 269                                 null;
 270                         when S_S_WRITE =>
 271                                 -- nur bei < 71 weiter machen
 272                                 -- Hint: '/=' billiger als '<'
 273                                 if unsigned(s_cnt_int) /= 71 then
 274                                         wr_next <= '1';
 275                                         address_next <= std_logic_vector(unsigned(pos_int) + unsigned(s_cnt_int));
 276                                         data_in_next <= s_char;
 277                                         s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1);
 278                                 else
 279                                         -- was_bs hier missbrauchen, um ein d_new_eingabe zu verhindern
 280                                         was_bs_next <= '1';
 281                                 end if;
 282                         when S_S_BS =>
 283                                 -- ab 1 darf nicht mehr dekrementiert werden
 284                                 addr_tmp := (others => '0');
 285                                 if unsigned(s_cnt_int) /= 1 then
 286                                         addr_tmp(hspalte'length - 1 downto 0) := std_logic_vector(unsigned(s_cnt_int) - 1);
 287                                         d_new_bs_next <= '1';
 288                                 else
 289                                         addr_tmp(hspalte'length - 1 downto 0) := s_cnt_int;
 290                                 end if;
 291                                 s_cnt_next <= addr_tmp(hspalte'length - 1 downto 0);
 292                                 wr_next <= '1';
 293                                 address_next <= std_logic_vector(unsigned(pos_int) + unsigned(addr_tmp));
 294                                 data_in_next <= (others => '0');
 295                                 was_bs_next <= '1';
 296                         when S_S_FIN =>
 297                                 s_cnt_next <= (0 => '1', others => '0');
 298                                 d_new_result_next <= '1';
 299                                 -- resetten der parser counter
 300                                 p_sp_read_next <= (others => '0');
 301                                 p_sp_write_next <= std_logic_vector(to_unsigned(71,p_sp_write_next'length));
 302                         when S_S_FIN_POSUP =>
 303                                 -- overflowcheck nach 50 berechnungen => wieder von vorne anfangen
 304                                 if pos_int = std_logic_vector(to_unsigned(H_RAM_SIZE-142,H_RAM_WIDTH)) then
 305                                         pos_next <= (others => '0');
 306                                 else
 307                                         pos_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(142,H_RAM_WIDTH));
 308                                 end if;
 309                         when S_S_CLEAR_NEXT0 =>
 310                                 -- die naechsten 142 bytes im speicher resetten
 311                                 wr_next <= '1';
 312                                 address_next <= std_logic_vector(unsigned(pos_int) + unsigned(s_cnt_int));
 313                                 data_in_next <= (others => '0');
 314                                 if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then
 315                                         s_cnt_next <= (0 => '1', others => '0');
 316                                 else
 317                                         s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1);
 318                                 end if;
 319                         when S_S_CLEAR_NEXT1 =>
 320                                 -- die naechsten 142 bytes im speicher resetten
 321                                 wr_next <= '1';
 322                                 address_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(71,H_RAM_WIDTH) + unsigned(s_cnt_int));
 323                                 data_in_next <= (others => '0');
 324                                 if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then
 325                                         s_cnt_next <= (0 => '1', others => '0');
 326                                 else
 327                                         s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1);
 328                                 end if;
 329                         when S_S_DONE =>
 330                                 s_done_next <= '1';
 331                                 if was_bs_int = '0' then
 332                                         d_new_eingabe_next <= '1';
 333                                 end if;
 334                                 if s_take = '0' then
 335                                         was_bs_next <= '0';
 336                                 end if;
 337
 338                         when S_D_INIT =>
 339                                 addr_tmp := (others => '0');
 340                                 addr_tmp(hzeile'length - 1 downto 0) := d_zeile;
 341                                 mul_tmp := std_logic_vector(unsigned(addr_tmp) * to_unsigned(71,H_RAM_WIDTH));
 342                                 addr_tmp := mul_tmp((addr_tmp'length - 1) downto 0);
 343                                 addr_tmp := std_logic_vector(unsigned(addr_tmp) + unsigned(d_spalte));
 344                                 address_next <= addr_tmp;
 345                                 d_new_eingabe_next <= '0';
 346                                 d_new_result_next <= '0';
 347                         when S_D_READ =>
 348                                 d_char_next <= data_out;
 349                                 d_done_next <= '1';
 350
 351                         when S_PC_INIT =>
 352                                 addr_tmp := (others => '0');
 353                                 addr_tmp(hzeile'length - 1 downto 0) := pc_zeile;
 354                                 mul_tmp := std_logic_vector(unsigned(addr_tmp) * to_unsigned(71,H_RAM_WIDTH));
 355                                 addr_tmp := mul_tmp((addr_tmp'length - 1) downto 0);
 356                                 addr_tmp := std_logic_vector(unsigned(addr_tmp) + unsigned(pc_spalte));
 357                                 address_next <= addr_tmp;
 358                                 pc_busy_next <= '1';
 359                         when S_PC_READ =>
 360                                 pc_char_next <= data_out;
 361                                 pc_done_next <= '1';
 362                         when S_P_READ =>
 363                                 wr_next <= '0';
 364                                 spalte_tmp := std_logic_vector(unsigned(p_sp_read_int) + 1);
 365                                 p_sp_read_next <= spalte_tmp;
 366                                 address_next <= std_logic_vector(unsigned(pos_int) + unsigned(spalte_tmp));
 367                         when S_P_READ_DONE =>
 368                                 p_rdone_next <= '1';
 369                                 p_read_next <= data_out;
 370
 371                         when S_P_WRITE =>
 372                                 wr_next <= '1';
 373                                 data_in_next <= p_write;
 374                                 spalte_tmp := std_logic_vector(unsigned(p_sp_write_int) - 1);
 375                                 p_sp_write_next <= spalte_tmp;
 376                                 address_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(71,H_RAM_WIDTH) + unsigned(spalte_tmp));
 377                         when S_P_WRITE_DONE =>
 378                                 p_wdone_next <= '1';
 379                         when S_P_DONE =>
 380                                 p_rdone_next <= '0';
 381                                 p_wdone_next <= '0';
 382                 end case;
 383         end process;
 384
 385         sp_ram_inst : entity work.sp_ram(beh)
 386         generic map (
 387                 ADDR_WIDTH => H_RAM_WIDTH
 388         )
 389         port map (
 390                 sys_clk => sys_clk,
 391                 address => address_int,
 392                 data_out => data_out,
 393                 wr => wr_int,
 394                 data_in => data_in_int
 395         );
 396 end architecture beh;