src/history.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use work.gen_pkg.all;
   5
   6 entity history is
   7         port (
   8                 sys_clk : in std_logic;
   9                 sys_res_n : in std_logic;
  10                 -- PC-komm
  11                 pc_get :  in std_logic;
  12                 pc_spalte : in hspalte;
  13                 pc_zeile : in hzeile;
  14                 pc_char : out hbyte;
  15                 pc_done : out std_logic;
  16                 -- Scanner
  17                 s_char : in hbyte;
  18                 s_take : in std_logic;
  19                 s_done : out std_logic;
  20                 s_backspace : in std_logic;
  21                 -- Display
  22                 d_new_eingabe : out std_logic;
  23                 d_new_result : out std_logic;
  24                 d_new_bs : out std_logic;
  25                 d_zeile : in hzeile;
  26                 d_spalte : in hspalte;
  27                 d_get : in std_logic;
  28                 d_done : out std_logic;
  29                 d_char : out hbyte;
  30                 -- Parser
  31                 p_rget : in std_logic;
  32                 p_rdone : out std_logic;
  33                 p_read : out hbyte;
  34                 p_wtake : in std_logic;
  35                 p_wdone : out std_logic;
  36                 p_write : in hbyte;
  37                 p_finished : in std_logic
  38         );
  39 end entity history;
  40
  41 architecture beh of history is
  42         type HISTORY_STATE is (SIDLE, S_S_INIT, S_S_WRITE, S_S_BS, S_S_DONE, S_S_FIN,
  43                 S_D_INIT, S_D_READ, S_S_FIN_POSUP, S_P_READ, S_P_READ_DONE, S_P_WRITE,
  44                 S_P_WRITE_DONE, S_P_DONE, S_INIT, S_S_CLEAR_NEXT0, S_S_CLEAR_NEXT1, S_PC_INIT, S_PC_READ);
  45         signal state_int, state_next : HISTORY_STATE;
  46         signal was_bs_int, was_bs_next : std_logic;
  47         signal pos_int, pos_next : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
  48         signal s_done_int, s_done_next : std_logic;
  49         signal s_cnt_int, s_cnt_next : hspalte;
  50         signal d_new_eingabe_int, d_new_eingabe_next : std_logic;
  51         signal d_new_result_int, d_new_result_next : std_logic;
  52         signal d_new_bs_int, d_new_bs_next: std_logic;
  53         signal d_done_int, d_done_next : std_logic;
  54         signal d_char_int, d_char_next : hbyte;
  55         signal p_rdone_int, p_rdone_next : std_logic;
  56         signal p_wdone_int, p_wdone_next : std_logic;
  57         signal p_read_int, p_read_next : hbyte;
  58         signal p_sp_read_int, p_sp_read_next : hspalte;
  59         signal p_sp_write_int, p_sp_write_next : hspalte;
  60         signal pc_char_next ,pc_char_int : hbyte;
  61         signal pc_done_next, pc_done_int : std_logic;
  62
  63         -- ram
  64         signal address_next, address_int : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
  65         signal data_out, data_in_next, data_in_int : hbyte;
  66         signal wr_next, wr_int : std_logic;
  67 begin
  68         s_done <= s_done_int;
  69         d_new_eingabe <= d_new_eingabe_int;
  70         d_new_result <= d_new_result_int;
  71         d_new_bs <= d_new_bs_int;
  72         d_done <= d_done_int;
  73         d_char <= d_char_int;
  74         p_rdone <= p_rdone_int;
  75         p_wdone <= p_wdone_int;
  76         p_read <= p_read_int;
  77
  78         process(sys_clk, sys_res_n)
  79         begin
  80                 if sys_res_n = '0' then
  81                         -- internal
  82                         state_int <= S_INIT;
  83                         was_bs_int <= '0';
  84                         pos_int <= (others => '0');
  85                         -- out
  86                         s_done_int <= '0';
  87                         s_cnt_int <= (0 => '1', others => '0');
  88                         d_new_result_int <= '0';
  89                         d_new_eingabe_int <= '0';
  90                         d_new_bs_int <= '0';
  91                         d_done_int <= '0';
  92                         d_char_int <= (others => '0');
  93                         p_rdone_int <= '0';
  94                         p_wdone_int <= '0';
  95                         p_read_int <= (others => '0');
  96                         p_sp_read_int <= (others => '0');
  97                         p_sp_write_int <= std_logic_vector(to_unsigned(71,p_sp_write_int'length));
  98
  99                         pc_char_int  <= (others => '0');
 100                         pc_done_int  <= '0';
 101
 102                         address_int <= (0 => '1', others => '0');
 103                         data_in_int <= x"00";
 104                         wr_int <= '0';
 105                 elsif rising_edge(sys_clk) then
 106                         -- internal
 107                         state_int <= state_next;
 108                         was_bs_int <= was_bs_next;
 109                         pos_int <= pos_next;
 110                         -- out
 111                         s_done_int <= s_done_next;
 112                         s_cnt_int <= s_cnt_next;
 113                         d_new_result_int <= d_new_result_next;
 114                         d_new_eingabe_int <= d_new_eingabe_next;
 115                         d_new_bs_int <= d_new_bs_next;
 116                         d_done_int <= d_done_next;
 117                         d_char_int <= d_char_next;
 118                         p_rdone_int <= p_rdone_next;
 119                         p_wdone_int <= p_wdone_next;
 120                         p_read_int <= p_read_next;
 121                         p_sp_read_int <= p_sp_read_next;
 122                         p_sp_write_int <= p_sp_write_next;
 123
 124                         pc_char_int <= pc_char_next;
 125                         pc_done_int <= pc_done_next;
 126
 127                         address_int <= address_next;
 128                         data_in_int <= data_in_next;
 129                         wr_int <= wr_next;
 130                 end if;
 131         end process;
 132
 133         -- next state
 134         process(state_int, d_get, pc_get, p_finished, s_take, s_backspace, was_bs_int,
 135                 p_rget, p_wtake, pos_int, s_cnt_int)
 136         begin
 137                 state_next <= state_int;
 138
 139                 case state_int is
 140                         when S_INIT =>
 141                                 -- ganzen speicher clearen: fuer ausgabe am vga nicht umbedingt
 142                                 -- noetig, aber spaetestens fuers dumpen per rs232
 143                                 if pos_int = std_logic_vector(to_unsigned(H_RAM_SIZE,H_RAM_WIDTH)) then
 144                                         state_next <= SIDLE;
 145                                 end if;
 146                         when SIDLE =>
 147                                 -- S_S_FIN: tmp..
 148                                 if s_take = '1' then
 149                                         state_next <= S_S_INIT;
 150                                 elsif p_rget = '1' then
 151                                         state_next <= S_P_READ;
 152                                 elsif p_wtake = '1' then
 153                                         state_next <= S_P_WRITE;
 154                                 elsif p_finished = '1' then
 155                                         state_next <= S_S_FIN;
 156                                 elsif d_get = '1' then
 157                                         state_next <= S_D_INIT;
 158                                 elsif pc_get = '1' then
 159                                         state_next <= S_PC_INIT;
 160                                 end if;
 161                         when S_S_INIT =>
 162                                 if s_backspace = '1' then
 163                                         state_next <= S_S_BS;
 164                                 else
 165                                         state_next <= S_S_WRITE;
 166                                 end if;
 167                         when S_S_WRITE =>
 168                                 state_next <= S_S_DONE;
 169                         when S_S_BS =>
 170                                 state_next <= S_S_DONE;
 171                         when S_S_FIN =>
 172                                 if p_finished = '0' then
 173                                         state_next <= S_S_FIN_POSUP;
 174                                 end if;
 175                         when S_S_FIN_POSUP =>
 176                                 state_next <= S_S_CLEAR_NEXT0;
 177                         when S_S_CLEAR_NEXT0 =>
 178                                 if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then
 179                                         state_next <= S_S_CLEAR_NEXT1;
 180                                 end if;
 181                         when S_S_CLEAR_NEXT1 =>
 182                                 if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then
 183                                         state_next <= SIDLE;
 184                                 end if;
 185                         when S_S_DONE =>
 186                                 if s_take = '0' then
 187                                         state_next <= SIDLE;
 188                                 end if;
 189
 190                         when S_D_INIT =>
 191                                 state_next <= S_D_READ;
 192                         when S_D_READ =>
 193                                 if d_get = '0' then
 194                                         state_next <= SIDLE;
 195                                 end if;
 196                         when S_PC_INIT =>
 197                                 state_next <= S_PC_READ;
 198                         when S_PC_READ =>
 199                                 if d_get = '0' then
 200                                         state_next <= SIDLE;
 201                                 end if;
 202                         when S_P_READ =>
 203                                 state_next <= S_P_READ_DONE;
 204                         when S_P_READ_DONE =>
 205                                 if p_rget = '0' then
 206                                         state_next <= S_P_DONE;
 207                                 end if;
 208                         when S_P_WRITE =>
 209                                 state_next <= S_P_WRITE_DONE;
 210                         when S_P_WRITE_DONE =>
 211                                 if p_wtake = '0' then
 212                                         state_next <= S_P_DONE;
 213                                 end if;
 214                         when S_P_DONE =>
 215                                 state_next <= SIDLE;
 216                 end case;
 217         end process;
 218
 219         -- out
 220         process(state_int, s_cnt_int, d_spalte, d_zeile, data_out, s_char, address_int,
 221                         data_in_int, d_new_result_int, d_new_eingabe_int, d_new_bs_int,
 222                         was_bs_int, s_take, pos_int, p_rdone_int, p_wdone_int, p_read_int,
 223                         p_write, p_sp_read_int, p_sp_write_int)
 224                 variable addr_tmp : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
 225                 variable spalte_tmp : hspalte;
 226                 variable mul_tmp : std_logic_vector((H_RAM_WIDTH*2) -1 downto 0);
 227         begin
 228                 s_done_next <= '0';
 229                 s_cnt_next <= s_cnt_int;
 230                 was_bs_next <= was_bs_int;
 231                 pos_next <= pos_int;
 232                 d_new_result_next <= d_new_result_int;
 233                 d_new_eingabe_next <= d_new_eingabe_int;
 234                 d_new_bs_next <= '0';
 235                 d_done_next <= '0';
 236                 d_char_next <= (others => '0');
 237                 wr_next <= '0';
 238                 address_next <= address_int;
 239                 data_in_next <= data_in_int;
 240                 pc_done <= '0';
 241                 pc_char <= (others => '0');
 242                 p_rdone_next <= p_rdone_int;
 243                 p_wdone_next <= p_wdone_int;
 244                 p_read_next <= p_read_int;
 245                 p_sp_read_next <= p_sp_read_int;
 246                 p_sp_write_next <= p_sp_write_int;
 247
 248                 case state_int is
 249                         when S_INIT =>
 250                                 wr_next <= '1';
 251                                 address_next <= pos_int;
 252                                 data_in_next <= (others => '0');
 253                                 if pos_int = std_logic_vector(to_unsigned(H_RAM_SIZE,H_RAM_WIDTH)) then
 254                                         pos_next <= (others => '0');
 255                                 else
 256                                         pos_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(1,H_RAM_WIDTH));
 257                                 end if;
 258                         when SIDLE =>
 259                                 d_new_result_next <= '0';
 260                         when S_S_INIT =>
 261                                 null;
 262                         when S_S_WRITE =>
 263                                 -- nur bei < 71 weiter machen
 264                                 -- Hint: '/=' billiger als '<'
 265                                 if unsigned(s_cnt_int) /= 71 then
 266                                         wr_next <= '1';
 267                                         address_next <= std_logic_vector(unsigned(pos_int) + unsigned(s_cnt_int));
 268                                         data_in_next <= s_char;
 269                                         s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1);
 270                                 else
 271                                         -- was_bs hier missbrauchen, um ein d_new_eingabe zu verhindern
 272                                         was_bs_next <= '1';
 273                                 end if;
 274                         when S_S_BS =>
 275                                 -- ab 1 darf nicht mehr dekrementiert werden
 276                                 addr_tmp := (others => '0');
 277                                 if unsigned(s_cnt_int) /= 1 then
 278                                         addr_tmp(hspalte'length - 1 downto 0) := std_logic_vector(unsigned(s_cnt_int) - 1);
 279                                         d_new_bs_next <= '1';
 280                                 else
 281                                         addr_tmp(hspalte'length - 1 downto 0) := s_cnt_int;
 282                                 end if;
 283                                 s_cnt_next <= addr_tmp(hspalte'length - 1 downto 0);
 284
 285                                 wr_next <= '1';
 286                                 address_next <= std_logic_vector(unsigned(pos_int) + unsigned(addr_tmp));
 287                                 data_in_next <= (others => '0');
 288                                 was_bs_next <= '1';
 289                         when S_S_FIN =>
 290                                 s_cnt_next <= (0 => '1', others => '0');
 291                                 d_new_result_next <= '1';
 292                                 -- resetten der parser counter
 293                                 p_sp_read_next <= (others => '0');
 294                                 p_sp_write_next <= std_logic_vector(to_unsigned(71,p_sp_write_next'length));
 295                         when S_S_FIN_POSUP =>
 296                                 -- overflowcheck nach 50 berechnungen => wieder von vorne anfangen
 297                                 if pos_int = std_logic_vector(to_unsigned(H_RAM_SIZE-142,H_RAM_WIDTH)) then
 298                                         pos_next <= (others => '0');
 299                                 else
 300                                         pos_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(142,H_RAM_WIDTH));
 301                                 end if;
 302                         when S_S_CLEAR_NEXT0 =>
 303                                 -- die naechsten 142 bytes im speicher resetten
 304                                 wr_next <= '1';
 305                                 address_next <= std_logic_vector(unsigned(pos_int) + unsigned(s_cnt_int));
 306                                 data_in_next <= (others => '0');
 307                                 if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then
 308                                         s_cnt_next <= (0 => '1', others => '0');
 309                                 else
 310                                         s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1);
 311                                 end if;
 312                         when S_S_CLEAR_NEXT1 =>
 313                                 -- die naechsten 142 bytes im speicher resetten
 314                                 wr_next <= '1';
 315                                 address_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(71,H_RAM_WIDTH) + unsigned(s_cnt_int));
 316                                 data_in_next <= (others => '0');
 317                                 if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then
 318                                         s_cnt_next <= (0 => '1', others => '0');
 319                                 else
 320                                         s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1);
 321                                 end if;
 322                         when S_S_DONE =>
 323                                 s_done_next <= '1';
 324                                 if was_bs_int = '0' then
 325                                         d_new_eingabe_next <= '1';
 326                                 end if;
 327                                 if s_take = '0' then
 328                                         was_bs_next <= '0';
 329                                 end if;
 330
 331                         when S_D_INIT =>
 332                                 addr_tmp := (others => '0');
 333                                 addr_tmp(hzeile'length - 1 downto 0) := d_zeile;
 334                                 mul_tmp := std_logic_vector(unsigned(addr_tmp) * to_unsigned(71,H_RAM_WIDTH));
 335                                 addr_tmp := mul_tmp((addr_tmp'length - 1) downto 0);
 336                                 addr_tmp := std_logic_vector(unsigned(addr_tmp) + unsigned(d_spalte));
 337                                 address_next <= addr_tmp;
 338                                 d_new_eingabe_next <= '0';
 339                                 d_new_result_next <= '0';
 340                         when S_D_READ =>
 341                                 d_char_next <= data_out;
 342                                 d_done_next <= '1';
 343
 344                         when S_PC_INIT =>
 345                                 addr_tmp := (others => '0');
 346                                 addr_tmp(hzeile'length - 1 downto 0) := pc_zeile;
 347                                 mul_tmp := std_logic_vector(unsigned(addr_tmp) * to_unsigned(71,H_RAM_WIDTH));
 348                                 addr_tmp := mul_tmp((addr_tmp'length - 1) downto 0);
 349                                 addr_tmp := std_logic_vector(unsigned(addr_tmp) + unsigned(pc_spalte));
 350                                 address_next <= addr_tmp;
 351                         when S_PC_READ =>
 352                                 pc_char_next <= data_out;
 353                                 pc_done_next <= '1';
 354                         when S_P_READ =>
 355                                 wr_next <= '0';
 356                                 spalte_tmp := std_logic_vector(unsigned(p_sp_read_int) + 1);
 357                                 p_sp_read_next <= spalte_tmp;
 358                                 address_next <= std_logic_vector(unsigned(pos_int) + unsigned(spalte_tmp));
 359                         when S_P_READ_DONE =>
 360                                 p_rdone_next <= '1';
 361                                 p_read_next <= data_out;
 362
 363                         when S_P_WRITE =>
 364                                 wr_next <= '1';
 365                                 data_in_next <= p_write;
 366                                 spalte_tmp := std_logic_vector(unsigned(p_sp_write_int) - 1);
 367                                 p_sp_write_next <= spalte_tmp;
 368                                 address_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(71,H_RAM_WIDTH) + unsigned(spalte_tmp));
 369                         when S_P_WRITE_DONE =>
 370                                 p_wdone_next <= '1';
 371                         when S_P_DONE =>
 372                                 p_rdone_next <= '0';
 373                                 p_wdone_next <= '0';
 374                 end case;
 375         end process;
 376
 377         sp_ram_inst : entity work.sp_ram(beh)
 378         generic map (
 379                 ADDR_WIDTH => H_RAM_WIDTH
 380         )
 381         port map (
 382                 sys_clk => sys_clk,
 383                 address => address_int,
 384                 data_out => data_out,
 385                 wr => wr_int,
 386                 data_in => data_in_int
 387         );
 388 end architecture beh;