src/display.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use work.gen_pkg.all;
   5 use work.textmode_vga_component_pkg.all;
   6 use work.textmode_vga_pkg.all;
   7 use work.textmode_vga_platform_dependent_pkg.all;
   8
   9 entity display is
  10         port (
  11                 sys_clk : in std_logic;
  12                 sys_res_n : in std_logic;
  13                 -- History
  14                 d_new_eingabe : in std_logic;
  15                 d_new_result : in std_logic;
  16                 d_zeile : out hzeile;
  17                 d_spalte : out hspalte;
  18                 d_get : out std_logic;
  19                 d_done : in std_logic;
  20                 d_char : in hbyte;
  21                 -- VGA
  22                 command : out std_logic_vector(7 downto 0);
  23                 command_data : out std_logic_vector(31 downto 0);
  24                 free : in std_logic
  25         );
  26 end entity display;
  27
  28 architecture beh of display is
  29         type DISPLAY_STATE is (SIDLE, S_NEW_RESULT, S_NEW_INPUT, S_COUNTUP, S_GETCH,
  30         S_PUTCH, S_WAIT, S_NOP1);
  31         signal state_int, state_next : DISPLAY_STATE;
  32         signal d_zeile_int, d_zeile_next : hzeile;
  33         signal d_spalte_int, d_spalte_next : hspalte;
  34         signal d_get_int, d_get_next : std_logic;
  35         signal command_int, command_next : std_logic_vector(7 downto 0);
  36         signal command_data_int, command_data_next : std_logic_vector(31 downto 0);
  37 begin
  38         d_zeile <= d_zeile_int;
  39         d_spalte <= d_spalte_int;
  40         d_get <= d_get_int;
  41         command <= command_int;
  42         command_data <= command_data_int;
  43
  44         process(sys_clk, sys_res_n)
  45         begin
  46                 if sys_res_n = '0' then
  47                         -- internal
  48                         state_int <= SIDLE;
  49                         -- out
  50                         d_zeile_int <= (others => '0');
  51                         d_spalte_int <= (others => '0');
  52                         d_get_int <= '0';
  53                         command_int <= COMMAND_NOP;
  54                         command_data_int <= (others => '0');
  55                 elsif rising_edge(sys_clk) then
  56                         -- internal
  57                         state_int <= state_next;
  58                         -- out
  59                         d_zeile_int <= d_zeile_next;
  60                         d_spalte_int <= d_spalte_next;
  61                         d_get_int <= d_get_next;
  62                         command_int <= command_next;
  63                         command_data_int <= command_data_next;
  64                 end if;
  65         end process;
  66
  67         -- next state
  68         process(state_int, d_new_result, d_new_eingabe, d_done, free, d_spalte_int,
  69                 d_char)
  70         begin
  71                 state_next <= state_int;
  72
  73                 case state_int is
  74                         when SIDLE =>
  75                                 if d_new_eingabe = '1' then
  76                                         state_next <= S_NEW_INPUT;
  77                                 end if;
  78                                 if d_new_result = '1' then
  79                                         state_next <= S_NEW_RESULT;
  80                                 end if;
  81                         when S_NEW_RESULT | S_NEW_INPUT =>
  82                                 state_next <= S_COUNTUP;
  83                         when S_COUNTUP =>
  84                                 state_next <= S_GETCH;
  85                         when S_GETCH =>
  86                                 if free = '1' and d_done = '1' then
  87                                         state_next <= S_PUTCH;
  88                                 end if;
  89                         when S_PUTCH =>
  90                                 if free = '0' or (free = '1' and d_char = x"00") then
  91                                         state_next <= S_WAIT;
  92                                 end if;
  93                         when S_WAIT =>
  94                                 if free = '1' and d_done = '0' then
  95                                         state_next <= S_NOP1;
  96                                 end if;
  97                         when S_NOP1 =>
  98                                 if free = '1' then
  99                                         if unsigned(d_spalte_int) = 71 then
 100                                                 state_next <= SIDLE;
 101                                         else
 102                                                 state_next <= S_COUNTUP;
 103                                         end if;
 104                                 end if;
 105                 end case;
 106         end process;
 107
 108         -- out
 109         process(state_int, d_zeile_int, d_spalte_int, d_get_int, command_int,
 110                 command_data_int, d_char)
 111         begin
 112                 d_zeile_next <= d_zeile_int;
 113                 d_spalte_next <= d_spalte_int;
 114                 d_get_next <= '0';
 115                 command_next <= command_int;
 116                 command_data_next <= command_data_int;
 117
 118                 case state_int is
 119                         when SIDLE =>
 120                                 null;
 121                         when S_NEW_INPUT =>
 122                                 d_spalte_next <= (others => '0');
 123                         when S_NEW_RESULT =>
 124                                 d_spalte_next <= (others => '0');
 125                                 case d_zeile_int is
 126                                         when "11111" => d_zeile_next <= "00000";
 127                                         when others => d_zeile_next <= std_logic_vector(unsigned(d_zeile_int) + 1);
 128                                 end case;
 129                         when S_COUNTUP =>
 130                                 d_get_next <= '1';
 131                                 d_spalte_next <= std_logic_vector(unsigned(d_spalte_int) + 1);
 132                         when S_GETCH =>
 133                                 d_get_next <= '1';
 134                         when S_PUTCH =>
 135                                 if d_char /= x"00" then
 136                                         command_next <= COMMAND_SET_CHAR;
 137                                         command_data_next <= x"ffffff" & std_logic_vector(d_char);
 138                                 end if;
 139                         when S_WAIT | S_NOP1 =>
 140                                 command_next <= COMMAND_NOP;
 141                                 command_data_next <= x"00000000";
 142                 end case;
 143         end process;
 144 end architecture beh;