2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
5 use work.textmode_vga_component_pkg.all;
6 use work.textmode_vga_pkg.all;
7 use work.textmode_vga_platform_dependent_pkg.all;
11 sys_clk : in std_logic;
12 sys_res_n : in std_logic;
14 d_new_eingabe : in std_logic;
15 d_new_result : in std_logic;
17 d_spalte : out hspalte;
18 d_get : out std_logic;
19 d_done : in std_logic;
22 command : out std_logic_vector(7 downto 0);
23 command_data : out std_logic_vector(31 downto 0);
28 architecture beh of display is
29 type DISPLAY_STATE is (S_INIT, SIDLE, S_NEW_RESULT, S_NEW_INPUT, S_COUNTUP, S_GETCH,
30 S_CR1, S_NL1, S_PUTCH1, S_PUTCH2, S_WAIT, S_NOP1);
31 signal state_int, state_next : DISPLAY_STATE;
32 signal d_zeile_int, d_zeile_next : hzeile;
33 signal d_spalte_int, d_spalte_next : hspalte;
34 signal d_get_int, d_get_next : std_logic;
35 signal command_int, command_next : std_logic_vector(7 downto 0);
36 signal command_data_int, command_data_next : std_logic_vector(31 downto 0);
38 d_zeile <= d_zeile_int;
39 d_spalte <= d_spalte_int;
41 command <= command_int;
42 command_data <= command_data_int;
44 process(sys_clk, sys_res_n)
46 if sys_res_n = '0' then
50 d_zeile_int <= (others => '0');
51 d_spalte_int <= (others => '0');
53 command_int <= COMMAND_NOP;
54 command_data_int <= (others => '0');
55 elsif rising_edge(sys_clk) then
57 state_int <= state_next;
59 d_zeile_int <= d_zeile_next;
60 d_spalte_int <= d_spalte_next;
61 d_get_int <= d_get_next;
62 command_int <= command_next;
63 command_data_int <= command_data_next;
68 process(state_int, d_new_result, d_new_eingabe, d_done, free, d_spalte_int,
71 state_next <= state_int;
77 if d_new_eingabe = '1' then
78 state_next <= S_NEW_INPUT;
80 if d_new_result = '1' then
81 state_next <= S_NEW_RESULT;
86 state_next <= S_COUNTUP;
93 state_next <= S_COUNTUP;
96 state_next <= S_GETCH;
98 if free = '1' and d_done = '1' and d_new_result = '0' and d_new_eingabe = '0' then
99 state_next <= S_PUTCH1;
102 state_next <= S_PUTCH2;
104 if free = '0' or (free = '1' and d_char = x"00") then
105 state_next <= S_WAIT;
108 if free = '1' and d_done = '0' then
109 state_next <= S_NOP1;
114 --if unsigned(d_spalte_int) = 71 then
115 -- state_next <= SIDLE;
117 -- state_next <= S_COUNTUP;
124 process(state_int, d_zeile_int, d_spalte_int, d_get_int, command_int,
125 command_data_int, d_char)
127 d_zeile_next <= d_zeile_int;
128 d_spalte_next <= d_spalte_int;
130 command_next <= command_int;
131 command_data_next <= command_data_int;
135 d_spalte_next <= (others => '0');
136 d_zeile_next <= (others => '0');
142 d_spalte_next <= (others => '0');
144 when "11111" => d_zeile_next <= "00000";
145 when others => d_zeile_next <= std_logic_vector(unsigned(d_zeile_int) + 1);
148 command_next <= COMMAND_SET_CHAR;
149 command_data_next <= x"ffffff" & x"0d"; -- carrige return
151 command_next <= COMMAND_SET_CHAR;
152 command_data_next <= x"ffffff" & x"0a"; -- newline
155 d_spalte_next <= std_logic_vector(unsigned(d_spalte_int) + 1);
159 if d_char /= x"00" then
160 command_next <= COMMAND_SET_CHAR;
161 command_data_next <= x"ffffff" & std_logic_vector(d_char);
163 when S_PUTCH2 => null;
164 when S_WAIT | S_NOP1 =>
165 command_next <= COMMAND_NOP;
166 command_data_next <= x"00000000";
169 end architecture beh;