display: quartus warning fix
[hwmod.git] / src / display.vhd
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4 use work.gen_pkg.all;
5 use work.textmode_vga_component_pkg.all;
6 use work.textmode_vga_pkg.all;
7 use work.textmode_vga_platform_dependent_pkg.all;
8
9 entity display is
10         port (
11                 sys_clk : in std_logic;
12                 sys_res_n : in std_logic;
13                 -- History
14                 d_new_eingabe : in std_logic;
15                 d_new_result : in std_logic;
16                 d_zeile : out hzeile;
17                 d_spalte : out hspalte;
18                 d_get : out std_logic;
19                 d_done : in std_logic;
20                 d_char : in hbyte;
21                 -- VGA
22                 command : out std_logic_vector(7 downto 0);
23                 command_data : out std_logic_vector(31 downto 0);
24                 free : in std_logic
25         );
26 end entity display;
27
28 architecture beh of display is
29         type DISPLAY_STATE is (SIDLE, S_NEW_RESULT, S_NEW_INPUT, S_COUNTUP, S_GETCH,
30         S_PUTCH, S_WAIT, S_NOP1, S_NOP2);
31         signal state_int, state_next : DISPLAY_STATE;
32         signal d_zeile_int, d_zeile_next : hzeile;
33         signal d_spalte_int, d_spalte_next : hspalte;
34         signal d_get_int, d_get_next : std_logic;
35         signal command_int, command_next : std_logic_vector(7 downto 0);
36         signal command_data_int, command_data_next : std_logic_vector(31 downto 0);
37 begin
38         d_zeile <= d_zeile_int;
39         d_spalte <= d_spalte_int;
40         d_get <= d_get_int;
41         command <= command_int;
42         command_data <= command_data_int;
43
44         process(sys_clk, sys_res_n)
45         begin
46                 if sys_res_n = '0' then
47                         -- internal
48                         state_int <= SIDLE;
49                         -- out
50                         d_zeile_int <= (others => '0');
51                         d_spalte_int <= (others => '0');
52                         d_get_int <= '0';
53                         command_int <= COMMAND_NOP;
54                         command_data_int <= (others => '0');
55                 elsif rising_edge(sys_clk) then
56                         -- internal
57                         state_int <= state_next;
58                         -- out
59                         d_zeile_int <= d_zeile_next;
60                         d_spalte_int <= d_spalte_next;
61                         d_get_int <= d_get_next;
62                         command_int <= command_next;
63                         command_data_int <= command_data_next;
64                 end if;
65         end process;
66
67         -- next state
68         process(state_int, d_new_result, d_new_eingabe, d_done, free, d_spalte_int)
69         begin
70                 state_next <= state_int;
71
72                 case state_int is
73                         when SIDLE =>
74                                 if d_new_eingabe = '1' then
75                                         state_next <= S_NEW_INPUT;
76                                 end if;
77                                 if d_new_result = '1' then
78                                         state_next <= S_NEW_RESULT;
79                                 end if;
80                         when S_NEW_RESULT | S_NEW_INPUT =>
81                                 state_next <= S_COUNTUP;
82                         when S_COUNTUP =>
83                                 state_next <= S_GETCH;
84                         when S_GETCH =>
85                                 if free = '1' and d_done = '1' then
86                                         state_next <= S_PUTCH;
87                                 end if;
88                         when S_PUTCH =>
89                                 if free = '0' then
90                                         state_next <= S_WAIT;
91                                 end if;
92                         when S_WAIT =>
93                                 if free = '1' and d_done = '0' then
94                                         state_next <= S_NOP1;
95                                 end if;
96                         when S_NOP1 =>
97                                 if free = '0' then
98                                         state_next <= S_NOP2;
99                                 end if;
100                         when S_NOP2 =>
101                                 if free = '1' then
102                                         if unsigned(d_spalte_int) = 71 then
103                                                 state_next <= SIDLE;
104                                         else
105                                                 state_next <= S_COUNTUP;
106                                         end if;
107                                 end if;
108                 end case;
109         end process;
110
111         -- out
112         process(state_int, d_zeile_int, d_spalte_int, d_get_int, command_int,
113                 command_data_int, d_char)
114         begin
115                 d_zeile_next <= d_zeile_int;
116                 d_spalte_next <= d_spalte_int;
117                 d_get_next <= '0';
118                 command_next <= command_int;
119                 command_data_next <= command_data_int;
120
121                 case state_int is
122                         when SIDLE =>
123                                 null;
124                         when S_NEW_INPUT =>
125                                 d_spalte_next <= (others => '0');
126                         when S_NEW_RESULT =>
127                                 d_spalte_next <= (others => '0');
128                                 case d_zeile_int is
129                                         when "11111" => d_zeile_next <= "00000";
130                                         when others => d_zeile_next <= std_logic_vector(unsigned(d_zeile_int) + 1);
131                                 end case;
132                         when S_COUNTUP =>
133                                 d_get_next <= '1';
134                                 d_spalte_next <= std_logic_vector(unsigned(d_spalte_int) + 1);
135                         when S_GETCH =>
136                                 d_get_next <= '1';
137                         when S_PUTCH =>
138                                 command_next <= COMMAND_SET_CHAR;
139                                 command_data_next <= x"000000" & std_logic_vector(d_char);
140                         when S_WAIT | S_NOP2 =>
141                                 null;
142                         when S_NOP1 =>
143                                 command_next <= COMMAND_NOP;
144                                 command_data_next <= x"00000000";
145                 end case;
146         end process;
147 end architecture beh;