2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
5 use work.textmode_vga_component_pkg.all;
6 use work.textmode_vga_pkg.all;
7 use work.textmode_vga_platform_dependent_pkg.all;
9 -- this is for test file io
12 entity beh_pc_communication_tb is
13 end entity beh_pc_communication_tb;
15 architecture sim of beh_pc_communication_tb is
16 type byte_file_type is file of hbyte;
17 signal sys_clk : std_logic;
18 signal sys_res_n : std_logic;
19 signal btn_a : std_logic;
20 signal tx_new : std_logic;
21 signal tx_done : std_logic;
22 signal rx_new : std_logic;
23 signal d_get : std_logic;
24 signal d_done : std_logic;
25 signal rx_data, tx_data : std_logic_vector(7 downto 0);
27 signal d_zeile : hzeile;
28 signal d_spalte : hspalte;
29 signal d_char : hbyte;
32 inst : entity work.pc_communication(beh)
35 sys_res_n => sys_res_n,
65 stub_history : process
66 file f : byte_file_type open read_mode is "../../src/pc_communication.test";
69 wait until rising_edge(d_get);
70 assert not endfile(f) report "test beendet" severity failure;
77 end process stub_history;
79 reset_and_button : process
82 -- we only simulate pressing of button a by now!
91 end process reset_and_button;