2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
5 use work.textmode_vga_component_pkg.all;
6 use work.textmode_vga_pkg.all;
7 use work.textmode_vga_platform_dependent_pkg.all;
9 -- this is for test file io
12 entity beh_pc_communication_tb is
13 end entity beh_pc_communication_tb;
15 architecture sim of beh_pc_communication_tb is
16 type byte_file_type is file of hbyte;
17 subtype my_string is string(1 to 720);
18 signal sys_clk : std_logic;
19 signal sys_res_n : std_logic;
20 signal btn_a : std_logic;
21 signal tx_new : std_logic;
22 signal tx_done : std_logic;
23 signal rx_new : std_logic;
24 signal pc_get : std_logic;
25 signal pc_done : std_logic;
26 signal pc_busy : std_logic;
27 signal rx_data, tx_data : std_logic_vector(7 downto 0);
29 signal pc_zeile : hzeile;
30 signal pc_spalte : hspalte;
31 signal pc_char : hbyte;
34 inst : entity work.pc_communication(beh)
37 sys_res_n => sys_res_n,
53 pc_spalte => pc_spalte,
68 stub_history : process
69 file f : text open read_mode is "../../src/pc_communication.test";
70 variable rb : character;
71 variable good : boolean;
73 variable buf : my_string;
76 pc_char <= (others => '0');
79 wait until sys_res_n = '1';
81 while not endfile (f) loop
85 while i < l'length loop
87 wait until rising_edge(pc_get);
90 pc_char <= (others => '0');
93 pc_char <= hbyte(std_logic_vector(to_unsigned(character'pos(buf(i)),8)));
101 assert not endfile(f) report "test beendet" severity failure;
102 end process stub_history;
107 wait until sys_res_n = '1';
110 wait until rising_edge(tx_new);
115 end process stub_uart;
117 reset_and_button : process
120 -- we only simulate pressing of button a by now!
123 rx_data <= ( others => '0');
134 --assert false report "test beendet" severity failure;
135 end process reset_and_button;
137 end architecture sim;