2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
5 use work.textmode_vga_component_pkg.all;
6 use work.textmode_vga_pkg.all;
7 use work.textmode_vga_platform_dependent_pkg.all;
9 -- this is for test file io
12 entity beh_pc_communication_tb is
13 end entity beh_pc_communication_tb;
15 architecture sim of beh_pc_communication_tb is
16 type byte_file_type is file of hbyte;
17 subtype my_string is string(1 to 720);
18 signal sys_clk : std_logic;
19 signal sys_res_n : std_logic;
20 signal btn_a : std_logic;
21 signal tx_new : std_logic;
22 signal tx_done : std_logic;
23 signal rx_new : std_logic;
24 signal d_get : std_logic;
25 signal d_done : std_logic;
26 signal rx_data, tx_data : std_logic_vector(7 downto 0);
28 signal d_zeile : hzeile;
29 signal d_spalte : hspalte;
30 signal d_char : hbyte;
33 inst : entity work.pc_communication(beh)
36 sys_res_n => sys_res_n,
66 stub_history : process
67 file f : text open read_mode is "../../src/pc_communication.test";
68 --variable rb : hbyte;
69 variable rb : character;
70 variable good : boolean;
72 variable buf : my_string;
75 --take control of the situation.
76 d_char <= (others => '0');
78 wait until sys_res_n = '1';
80 while not endfile (f) loop
84 while i < l'length loop
86 wait until rising_edge(d_get);
87 d_char <= (others => '0');
90 d_char <= hbyte(std_logic_vector(to_unsigned(character'pos(buf(i)),8)));
98 assert not endfile(f) report "test beendet" severity failure;
99 end process stub_history;
104 wait until sys_res_n = '1';
107 wait until rising_edge(tx_new);
112 end process stub_uart;
114 reset_and_button : process
117 -- we only simulate pressing of button a by now!
120 tx_data <= ( others => '0');
121 rx_data <= ( others => '0');
132 --assert false report "test beendet" severity failure;
133 end process reset_and_button;
135 end architecture sim;