2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
6 entity beh_loopback_tb is
7 end entity beh_loopback_tb;
9 architecture sim of beh_loopback_tb is
10 constant CLK_FREQ : integer := 33000000;
11 constant BAUDRATE : integer := 115200;
12 constant BAUD : integer := CLK_FREQ/BAUDRATE;
14 signal sys_clk, sys_res_n, rxd, rx_new : std_logic;
15 signal rx_data : std_logic_vector (7 downto 0);
16 signal txd, tx_new, tx_done : std_logic;
17 signal tx_data : std_logic_vector (7 downto 0);
18 signal stop : boolean := false;
20 inst_rx : entity work.uart_rx(beh)
27 sys_res_n => sys_res_n,
32 inst_tx : entity work.uart_tx(beh)
39 sys_res_n => sys_res_n,
58 procedure exec_tc(testnr : integer;
59 constant testvector : std_logic_vector(9 downto 0);
60 constant expectedresult : std_logic_vector(7 downto 0)) is
62 -- vorher auf high setzen um falling edge simulieren zu koennen
67 rxd <= testvector(9-i);
69 icwait(sys_clk, BAUD);
73 wait until rx_new = '1';
74 if expectedresult = rx_data then
75 report "testfall " & integer'image(testnr) & " war erfolgreich";
77 report "testfall " & integer'image(testnr) & " schlug fehl";
82 wait until tx_done = '1';
84 wait until tx_done = '0';
88 variable testvector : std_logic_vector(9 downto 0);
89 variable expectedresult : std_logic_vector(7 downto 0);
94 tx_data <= (others => '0');
99 -- 1. parameter: testfallnummer
100 -- 2. parameter: STARTBIT (1 bit) - immer '0' | 8 DATENBITS | 1 STOPBIT - immer '1'
101 -- 3. parameter: byte das rauskommen soll
102 exec_tc(1, b"0000011111", b"11110000");
103 exec_tc(2, b"0101010101", b"01010101");
104 exec_tc(3, b"0110011001", b"00110011");
105 exec_tc(4, b"0001100111", b"11001100");
106 exec_tc(5, b"0010101011", b"10101010");
107 exec_tc(6, b"0100110111", b"11011001");