2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
5 use work.textmode_vga_component_pkg.all;
6 use work.textmode_vga_pkg.all;
7 use work.textmode_vga_platform_dependent_pkg.all;
9 entity beh_history_tb is
10 end entity beh_history_tb;
12 architecture sim of beh_history_tb is
14 signal sys_clk, sys_res_n : std_logic;
16 signal d_new_eingabe, d_new_result, d_new_bs : std_logic;
17 signal d_zeile : hzeile;
18 signal d_spalte : hspalte;
19 signal d_get, d_done : std_logic;
20 signal d_char : hbyte;
22 signal s_char : hbyte;
23 signal s_take, s_done, s_backspace : std_logic;
25 signal new_data : std_logic;
26 signal data : std_logic_vector(7 downto 0);
28 signal free : std_logic;
29 signal command : std_logic_vector(COMMAND_SIZE - 1 downto 0);
30 signal command_data : std_logic_vector(3 * COLOR_SIZE + CHAR_SIZE -1 downto 0);
32 signal p_rget : std_logic;
33 signal p_rdone : std_logic;
34 signal p_read : hbyte;
35 signal p_wtake : std_logic;
36 signal p_wdone : std_logic;
37 signal p_write : hbyte;
38 signal p_finished : std_logic;
40 signal do_it, finished : std_logic;
42 signal tx_data : std_logic_vector(7 downto 0);
43 signal tx_new, tx_done, txd : std_logic;
45 signal pc_zeile : hzeile;
46 signal pc_spalte : hspalte;
47 signal pc_get, pc_done : std_logic;
48 signal pc_char : hbyte;
49 signal pc_busy : std_logic;
51 signal btn_a_int : std_logic;
54 signal tx_debug : character;
56 signal stop : boolean := false;
59 inst : entity work.history(beh)
62 sys_res_n => sys_res_n,
67 s_backspace => s_backspace,
69 d_new_eingabe => d_new_eingabe,
70 d_new_result => d_new_result,
84 p_finished => p_finished,
87 pc_spalte => pc_spalte,
95 inst_disp : entity work.display(beh)
98 sys_res_n => sys_res_n,
100 d_new_eingabe => d_new_eingabe,
101 d_new_result => d_new_result,
102 d_new_bs => d_new_bs,
104 d_spalte => d_spalte,
110 command_data => command_data,
115 inst_parser : entity work.parser(beh)
118 sys_res_n => sys_res_n,
126 p_finished => p_finished,
133 inst_scan : entity work.scanner(beh)
136 sys_res_n => sys_res_n,
138 new_data => new_data,
144 s_backspace => s_backspace,
150 inst_uart : entity work.uart_tx(beh)
153 sys_res_n => sys_res_n,
161 inst_pc_com : entity work.pc_communication(beh)
164 sys_res_n => sys_res_n,
172 rx_data => (others => '0'),
175 pc_zeile => pc_zeile,
176 pc_spalte => pc_spalte,
182 tx_debug <= character'val(to_integer(unsigned(tx_data)));
209 file f : text open read_mode is "../../src/history.test";
212 variable input : string(1 to 100);
214 variable run_tc, run_inner : boolean := true;
215 variable i, j, y : natural;
220 data <= (others => '0');
226 f_loop : while not endfile(f) loop
227 data <= (others => '0');
229 f1_loop : while not endfile(f) loop
231 input := (others => nul);
232 if (l'length <= 100) then
233 input(1 to l'length) := l.all;
234 if (input(1) = '#') then
240 report "fehler in history.test: eingabe zu lange in testfall " & natural'image(i);
245 report "testcase(" & natural'image(i) & ").input: " & input;
252 mainl : while run_tc loop
258 assert(false) report "wtf @ schleife";
265 when nul => data <= ascii2sc(x"1c"); -- $ (enter)
266 when '!' => data <= ascii2sc(x"0e"); -- ! (backspace)
274 when others => data <= ascii2sc(std_logic_vector(to_unsigned(character'pos(input(j)),8)));
277 -- ack'en skippen, falls es ein "spezielles" zeichen ist (steht
278 -- in abhaengigkeit zum vorherigen zeichen)
279 if(not valid_char(data)) then
283 -- wuenschswert waere das hier:
284 -- > wait on s_backspace, s_take, do_it;
285 -- geht aber leider nicht, weil sich die signale vllt schon
288 main_inner : while run_inner loop
292 if s_backspace = '1' or s_take = '1' then
294 wait on s_take; -- = '0'
296 elsif do_it = '1' then
297 -- dauert normalweiser noch laenger (parser braucht
300 wait on do_it; -- = '0'
301 icwait(sys_clk, 850);
305 -- assert(false) report "history_tb: kann passieren. wenn tb haengt, dann hier auskommentieren";
310 report "==================";
313 icwait(sys_clk, 850);
318 btn_pressed : process is
321 wait until sys_res_n = '1';
322 wait for 50000 * 15 ns;
323 wait until rising_edge(sys_clk);
328 end process btn_pressed;
329 end architecture sim;