src/beh_history_tb.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use work.gen_pkg.all;
   5
   6 entity beh_history_tb is
   7 end entity beh_history_tb;
   8
   9 architecture sim of beh_history_tb is
  10         -- system
  11         signal sys_clk, sys_res_n : std_logic;
  12         -- history/display
  13         signal d_new_eingabe, d_new_result : std_logic;
  14         signal d_zeile : hzeile;
  15         signal d_spalte : hspalte;
  16         signal d_get, d_done : std_logic;
  17         signal d_char : hbyte;
  18         -- history/scanner
  19         signal s_char : hbyte;
  20         signal s_take, s_done, s_backspace : std_logic;
  21
  22         -- tmp: history<>scanner
  23         signal do_it, finished : std_logic;
  24
  25         signal stop : boolean := false;
  26 begin
  27         -- history
  28         inst : entity work.history(beh)
  29         port map (
  30                 sys_clk => sys_clk,
  31                 sys_res_n => sys_res_n,
  32                 -- scanner
  33                 s_char => s_char,
  34                 s_take => s_take,
  35                 s_done => s_done,
  36                 s_backspace => s_backspace,
  37                 -- display
  38                 d_new_eingabe => d_new_eingabe,
  39                 d_new_result => d_new_result,
  40                 d_zeile => d_zeile,
  41                 d_spalte => d_spalte,
  42                 d_get => d_get,
  43                 d_done => d_done,
  44                 d_char => d_char,
  45                 -- TODO: tmp only!
  46                 do_it => do_it,
  47                 finished => finished
  48         );
  49
  50         process
  51         begin
  52                 sys_clk <= '0';
  53                 wait for 15 ns;
  54                 sys_clk <= '1';
  55                 wait for 15 ns;
  56                 if stop = true then
  57                         wait;
  58                 end if;
  59         end process;
  60
  61         process
  62                 variable input : hstring := "12345678                                                                ";
  63                 variable ctmp : character;
  64
  65                 variable checkall : boolean := true;
  66                 variable i : integer := 1;
  67                 variable j : integer;
  68         begin
  69                 -- init & reset
  70                 sys_res_n <= '0';
  71                 s_char <= x"00";
  72                 s_take <= '0';
  73                 s_backspace <= '0';
  74                 d_zeile <= (others => '0');
  75                 d_spalte <= (others => '0');
  76                 d_get <= '0';
  77                 do_it <= '0';
  78
  79                 icwait(sys_clk, 5);
  80                 sys_res_n <= '1';
  81
  82                 while i <= 10 loop
  83                         s_take <= '1';
  84                         ctmp := input(i);
  85                         s_char <= hbyte(to_unsigned(character'pos(ctmp),8));
  86                         wait on s_done;
  87                         s_take <= '0';
  88                         wait on d_new_eingabe;
  89                         icwait(sys_clk, 2);
  90                         j := 1;
  91                         while j <= i loop
  92                                 d_spalte <= std_logic_vector(to_unsigned(j,7));
  93                                 d_zeile <= (others => '0');
  94                                 d_get <= '1';
  95                                 wait on d_done;
  96                                 icwait(sys_clk, 1);
  97                                 if d_char /= hbyte(to_unsigned(character'pos(input(j)),8)) then
  98                                         assert(false) report "passt nicht? d_char: "
  99                                         & character'val(to_integer(unsigned(d_char))) & ", solte sein: "
 100                                         & input(j);
 101                                         checkall := false;
 102                                 end if;
 103                                 d_get <= '0';
 104                                 icwait(sys_clk, 2);
 105                                 j := j + 1;
 106                         end loop;
 107                         i := i + 1;
 108                 end loop;
 109
 110                 do_it <= '1';
 111                 wait on finished;
 112                 icwait(sys_clk, 2);
 113                 do_it <= '0';
 114
 115
 116                 if checkall then
 117                         report "alle testfaelle der History waren erfolgreich!";
 118                 else
 119                         report "einige testfaelle schlugen fehl";
 120                 end if;
 121                 icwait(sys_clk, 10);
 122                 stop <= true;
 123                 wait;
 124         end process;
 125 end architecture sim;