2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
9 architecture sim of beh_alu_tb is
10 signal sys_clk, sys_res_n, do_calc, calc_done : std_logic;
11 signal opcode : alu_ops;
12 signal op1, op2, op3 : csigned;
13 signal stop : boolean := false;
15 inst : entity work.alu(beh)
19 sys_res_n => sys_res_n,
21 calc_done => calc_done,
40 type alu_testv is record
47 -- ggf. groesse des arrays erhoehen
48 type alu_testv_array is array (natural range 0 to 30) of alu_testv;
50 variable testmatrix : alu_testv_array :=
51 ( 0 => (-5, ALU_DIV, 3, -1),
52 1 => (7, ALU_ADD, 3, 10),
53 2 => (7, ALU_SUB, 1, 6),
54 3 => (7, ALU_DIV, 1, 7),
55 4 => (7, ALU_DIV, 3, 2),
56 5 => (7, ALU_ADD, 1, 8),
57 6 => (7, ALU_MUL, 3, 21),
58 7 => (-7, ALU_MUL, 3, -21),
59 8 => (268435456, ALU_MUL, -2, -536870912),
60 9 => (268435456, ALU_MUL, 2**5, 0), -- um fuenf nach links shiften
61 10 => (268435456 + 5, ALU_MUL, 2**5, 160), -- = 5 * (2^5)
62 11 => (100, ALU_DIV, 10, 10),
63 12 => (100, ALU_DIV, 51, 1),
64 13 => (100, ALU_DIV, 49, 2),
65 14 => (153156, ALU_DIV, 3543, 43),
66 15 => (-153156, ALU_DIV, 3543, -43),
67 16 => (153156, ALU_DIV, -3543, -43),
68 17 => (-153156, ALU_DIV, -3543, 43),
69 others => (0, ALU_ADD, 0, 0)
71 variable checkall : boolean := true;
77 op1 <= (others => '0');
78 op2 <= (others => '0');
83 for i in testmatrix'range loop
85 op1 <= to_signed(testmatrix(i).o1,CBITS);
86 opcode <= testmatrix(i).o;
87 op2 <= to_signed(testmatrix(i).o2,CBITS);
89 -- berechnung kann los gehen
92 -- warten auf die alu einheit
96 assert op3 = to_signed(testmatrix(i).expected,CBITS)
97 report "" & cinteger'image(testmatrix(i).o1) &
98 " " & integer'image(to_integer(signed(opcode))) &
99 " " & cinteger'image(testmatrix(i).o2) &
100 "/= " & integer'image(to_integer(op3)) &
101 " -- erwartet: " & cinteger'image(testmatrix(i).expected);
103 if op3 /= to_signed(testmatrix(i).expected,CBITS) then
113 report "alle testfaelle der ALU waren erfolgreich!";
115 report "nicht alle testfaelle der ALU waren erfolgreich!";
120 end architecture sim;